公开(公告)号：US07283471B2

公开(公告)日：2007-10-16

申请号：US10386642

申请日：2003-03-11

申请人： Maria C. Gutierrez ,  Shawn Adam Clayton ,  David R. Follett ,  Harold E. Roman ,  Nitin D. Godiwala ,  Richard F. Prohaska ,  James B. Williams

发明人： Maria C. Gutierrez ,  Shawn Adam Clayton ,  David R. Follett ,  Harold E. Roman ,  Nitin D. Godiwala ,  Richard F. Prohaska ,  James B. Williams

IPC分类号： H04L1/00

CPC分类号： H04L12/5602 ,  H04L47/10 ,  H04L47/16 ,  H04L47/263 ,  H04L47/30 ,  H04L2012/5635 ,  H04L2012/5651 ,  H04L2012/5682 ,  H04Q11/0478

摘要： A system includes a plurality of computers interconnected by a network including one or more switching nodes. The computers transfer messages over virtual circuits established thereamong. A computer, as a source computer for one or more virtual circuit(s), schedules transmission of messages on a round-robin basis as among the virtual circuits for which it is source computer. Each switching node which forms part of a path for respective virtual circuits also forwards messages for virtual circuits in a round-robin manner, and, a computer, as a destination computer for one or more virtual circuit(s), schedules processing of received messages in a round-robin manner. Round-robin transmission, forwarding and processing at the destination provides a degree of fairness in message transmission as among the virtual circuits established over the network. In addition, messages are transmitted in one or more cells, with the round-robin transmission being on a cell basis, so as to reduce delays which may occur for short messages if a long messages were transmitted in full for one virtual circuit before beginning transmission of a short message for another virtual circuit. For each virtual circuit, the destination computer and each switching node along the path for the virtual circuit can generate a virtual circuit flow control message for transmission to the source computer to temporarily limit transmission over the virtual circuit if the amount of resources being taken up by messages for the virtual circuit exceeds predetermined thresholds, further providing fairness as among the virtual circuits. In addition, each switching node or computer can generate link flow control messages for transmission to neighboring devices in the network to temporarily limit transmission thereto if the amount of resources taken up by all virtual circuits exceeds predetermined thresholds, so as to reduce the likelihood of message loss.

公开(公告)号：US06570850B1

公开(公告)日：2003-05-27

申请号：US09065118

申请日：1998-04-23

申请人： Maria C. Gutierrez ,  Shawn A. Clayton ,  David R. Follett ,  Nitin D. Godiwala ,  Richard F. Prohaska ,  Harold E. Roman ,  James B. Williams

发明人： Maria C. Gutierrez ,  Shawn A. Clayton ,  David R. Follett ,  Nitin D. Godiwala ,  Richard F. Prohaska ,  Harold E. Roman ,  James B. Williams

IPC分类号： H04Q1104

CPC分类号： H04L12/5602 ,  H04L47/10 ,  H04L47/16 ,  H04L47/263 ,  H04L47/30 ,  H04L2012/5635 ,  H04L2012/5651 ,  H04L2012/5682 ,  H04Q11/0478

摘要： A system includes a plurality of computers interconnected by a network including one or more switching nodes. The computers transfer messages over virtual circuits established thereamong. A computer, as a source computer for one or more virtual circuit(s), schedules transmission of messages on a round-robin basis as among the virtual circuits for which it is source computer. Each switching node which forms part of a path for respective virtual circuits also forwards messages for virtual circuits in a round-robin manner, and, a computer, as a destination computer for one or more virtual circuit(s), schedules processing of received messages in a round-robin manner. Round-robin transmission, forwarding and processing at the destination provides a degree of fairness in message transmission as among the virtual circuits established over the network. In addition, messages are transmitted in one or more cells, with the round-robin transmission being on a cell basis, so as to reduce delays which may occur for short messages if a long messages were transmitted in full for one virtual circuit before beginning transmission of a short message for another virtual circuit. For each virtual circuit, the destination computer and each switching node along the path for the virtual circuit can generate a virtual circuit flow control message for transmission to the source computer to temporarily limit transmission over the virtual circuit if the amount of resources being taken up by messages for the virtual circuit exceeds predetermined thresholds, further providing fairness as among the virtual circuits. In addition, each switching node or computer can generate link flow control messages for transmission to neighboring devices in the network to temporarily limit transmission thereto if the amount of resources taken up by all virtual circuits exceeds predetermined thresholds, so as to reduce the likelihood of message loss.

公开(公告)号：US07295557B2

公开(公告)日：2007-11-13

申请号：US10841009

申请日：2004-05-07

申请人： Shawn A. Clayton ,  David R. Follett ,  Nitin D. Godiwala ,  Maria C. Gutierrez ,  David S. Wells ,  James B. Williams

发明人： Shawn A. Clayton ,  David R. Follett ,  Nitin D. Godiwala ,  Maria C. Gutierrez ,  David S. Wells ,  James B. Williams

IPC分类号： H04L12/56

CPC分类号： H04L49/901 ,  H04L47/50 ,  H04L47/6215 ,  H04L47/6225 ,  H04L49/9078

摘要： A system includes a plurality of computers interconnected by a network including one or more switching nodes. The computers transfer messages over virtual circuits established thereamong. A computer, as a source computer for one or more virtual circuit(s), schedules transmission of messages on a round-robin basis as among the virtual circuits for which it is source computer. Each switching node which forms part of a path for respective virtual circuits also forwards messages for virtual circuits in a round-robin manner, and, a computer, as a destination computer for one or more virtual circuit(s), schedules processing of received messages in a round-robin manner. Round-robin transmission, forwarding and processing at the destination provides a degree of fairness in message transmission as among the virtual circuits established over the network. In addition, messages are transmitted in one or more cells, with the round-robin transmission being on a cell basis, so as to reduce delays which may occur for short messages if a long messages were transmitted in full for one virtual circuit before beginning transmission of a short message for another virtual circuit. For each virtual circuit, the destination computer and each switching node along the path for the virtual circuit can generate a virtual circuit flow control message for transmission to the source computer to temporarily limit transmission over the virtual circuit if the amount of resources being taken up by messages for the virtual circuit exceeds predetermined thresholds, further providing fairness as among the virtual circuits. In addition, each switching node or computer can generate link flow control messages for transmission to neighboring devices in the network to temporarily limit transmission thereto if the amount of resources taken up by all virtual circuits exceeds predetermined thresholds, so as to reduce the likelihood of message loss.

公开(公告)号：US06795442B1

公开(公告)日：2004-09-21

申请号：US09065115

申请日：1998-04-23

申请人： Shawn A. Clayton ,  David R. Follett ,  Nitin D. Godiwala ,  Maria C. Gutierrez ,  David S. Wells ,  James B. Williams

发明人： Shawn A. Clayton ,  David R. Follett ,  Nitin D. Godiwala ,  Maria C. Gutierrez ,  David S. Wells ,  James B. Williams

IPC分类号： H04L1228

CPC分类号： H04L49/901 ,  H04L47/50 ,  H04L47/6215 ,  H04L47/6225 ,  H04L49/9078

摘要： A system includes interconnected computers and switching nodes. A source computer for the virtual circuits schedules message transmissions on a round-robin basis. Each switching node also forwards messages in a round-robin manner, and a destination computer schedules processing of received messages in a round-robin manner. In addition, messages are transmitted in cells to reduce delays in short messages if long messages are transmitted for one virtual circuit before transmission of a short message for another virtual circuit. For each virtual circuit, the destination computer and each switching node can generate a virtual circuit flow control message to temporarily limit transmissions if the resources being taken up by messages exceed predetermined thresholds. In addition, each switching node or computer can generate link flow control messages for transmission to neighboring devices to temporarily limit transmissions if the resources taken up by all virtual circuits exceeds predetermined thresholds.

摘要翻译： 系统包括互连的计算机和交换节点。 用于虚拟电路的源计算机以轮询为基础来调度消息传输。 每个交换节点还以循环方式转发消息，并且目的地计算机以循环方式调度所接收的消息的处理。 另外，在发送用于另一个虚拟电路的短消息之前，如果在一个虚拟电路发送长消息，则在小区中发送消息以减少短消息中的延迟。 对于每个虚拟电路，目的地计算机和每个交换节点可以生成虚拟电路流控制消息，以便如果被消息占用的资源超过预定阈值，则临时限制传输。 此外，如果所有虚拟电路占用的资源超过预定阈值，则每个交换节点或计算机可以生成用于传输到相邻设备的链路流控制消息，以临时限制传输。

公开(公告)号：US6094712A

公开(公告)日：2000-07-25

申请号：US762186

申请日：1996-12-04

申请人： David R. Follett ,  Maria C. Gutierrez ,  Richard F. Prohaska

发明人： David R. Follett ,  Maria C. Gutierrez ,  Richard F. Prohaska

IPC分类号： G06F13/12 ,  G06F9/46 ,  G06F12/10 ,  G06F13/00 ,  H04L12/56 ,  H04Q11/04 ,  G06F12/00

CPC分类号： G06F9/546 ,  G06F12/1081 ,  H04Q11/0478 ,  H04L2012/5616 ,  H04L2012/5652 ,  H04L2012/5681

摘要： A computer interface system for communicating between computers along designated circuits is provided. An interface unit is provided in each host computer. Each unit includes a memory map that stores a map of physical addresses that correspond to virtual addresses for each application involved in a communication link. Each transfer of data is designated by a circuit that is established using the ATM protocol. The circuit is recognized by each unit involved in the communication and facilitates direct access of each host computer's main memory with minimum intervention from the operating system. A novel dynamic buffer management system is also provided.

摘要翻译： 提供了一种用于沿着指定电路在计算机之间进行通信的计算机接口系统。 在每个主机中提供接口单元。 每个单元包括存储映射，存储对应于通信链路中涉及的每个应用的虚拟地址的物理地址的映射。 每个数据传输由使用ATM协议建立的电路指定。 电路被通信中涉及的每个单元识别，并且可以通过操作系统的最小干预来促进每台主机的主存储器的直接访问。 还提供了一种新颖的动态缓冲管理系统。