公开(公告)号：US07673074B1

公开(公告)日：2010-03-02

申请号：US10421495

申请日：2003-04-22

申请人： Bino J. Sebastian ,  James B. Williams ,  Harold E. Roman ,  Richard F. Prohaska

发明人： Bino J. Sebastian ,  James B. Williams ,  Harold E. Roman ,  Richard F. Prohaska

IPC分类号： G06F15/16 ,  G06F15/173 ,  G06F15/177

CPC分类号： H04L69/16 ,  H04L69/12 ,  H04L69/161

摘要： The avoidance of port collisions in a hardware-accelerated network protocol, such as Transmission Control Protocol (TCP)/Internet Protocol (IP), is disclosed. In one example, a hardware-accelerated host bus adaptor (HBA) offloads protocol processing from a host computer's operating system. However, a port collision occurs if a non-accelerated host TCP/IP stack and a hardware accelerated host bus adapter TCP/IP stack choose the same port for establishing a network connection. In a double-ended TCP/IP acceleration connection, a unique TCP port is bound to the accelerated TCP/IP stack. In a single-ended TCP/IP acceleration connection, either the host TCP/IP stack is prevented from using that port or a non-accelerated connection is associated with an accelerated connection without binding a port.

摘要翻译： 披露了在硬件加速网络协议（如传输控制协议（TCP）/网际协议（IP））中避免端口冲突。 在一个示例中，硬件加速主机总线适配器（HBA）从主机的操作系统卸载协议处理。 但是，如果非加速主机TCP / IP堆栈和硬件加速主机总线适配器TCP / IP堆栈选择相同的端口建立网络连接，则会发生端口冲突。 在双端TCP / IP加速连接中，唯一的TCP端口绑定到加速TCP / IP堆栈。 在单端TCP / IP加速连接中，禁止主机TCP / IP堆栈使用该端口，或者非加速连接与加速连接相关联，而不绑定端口。

公开(公告)号：US07283471B2

公开(公告)日：2007-10-16

申请号：US10386642

申请日：2003-03-11

申请人： Maria C. Gutierrez ,  Shawn Adam Clayton ,  David R. Follett ,  Harold E. Roman ,  Nitin D. Godiwala ,  Richard F. Prohaska ,  James B. Williams

发明人： Maria C. Gutierrez ,  Shawn Adam Clayton ,  David R. Follett ,  Harold E. Roman ,  Nitin D. Godiwala ,  Richard F. Prohaska ,  James B. Williams

IPC分类号： H04L1/00

CPC分类号： H04L12/5602 ,  H04L47/10 ,  H04L47/16 ,  H04L47/263 ,  H04L47/30 ,  H04L2012/5635 ,  H04L2012/5651 ,  H04L2012/5682 ,  H04Q11/0478

摘要： A system includes a plurality of computers interconnected by a network including one or more switching nodes. The computers transfer messages over virtual circuits established thereamong. A computer, as a source computer for one or more virtual circuit(s), schedules transmission of messages on a round-robin basis as among the virtual circuits for which it is source computer. Each switching node which forms part of a path for respective virtual circuits also forwards messages for virtual circuits in a round-robin manner, and, a computer, as a destination computer for one or more virtual circuit(s), schedules processing of received messages in a round-robin manner. Round-robin transmission, forwarding and processing at the destination provides a degree of fairness in message transmission as among the virtual circuits established over the network. In addition, messages are transmitted in one or more cells, with the round-robin transmission being on a cell basis, so as to reduce delays which may occur for short messages if a long messages were transmitted in full for one virtual circuit before beginning transmission of a short message for another virtual circuit. For each virtual circuit, the destination computer and each switching node along the path for the virtual circuit can generate a virtual circuit flow control message for transmission to the source computer to temporarily limit transmission over the virtual circuit if the amount of resources being taken up by messages for the virtual circuit exceeds predetermined thresholds, further providing fairness as among the virtual circuits. In addition, each switching node or computer can generate link flow control messages for transmission to neighboring devices in the network to temporarily limit transmission thereto if the amount of resources taken up by all virtual circuits exceeds predetermined thresholds, so as to reduce the likelihood of message loss.

公开(公告)号：US06570850B1

公开(公告)日：2003-05-27

申请号：US09065118

申请日：1998-04-23

申请人： Maria C. Gutierrez ,  Shawn A. Clayton ,  David R. Follett ,  Nitin D. Godiwala ,  Richard F. Prohaska ,  Harold E. Roman ,  James B. Williams

发明人： Maria C. Gutierrez ,  Shawn A. Clayton ,  David R. Follett ,  Nitin D. Godiwala ,  Richard F. Prohaska ,  Harold E. Roman ,  James B. Williams

IPC分类号： H04Q1104

CPC分类号： H04L12/5602 ,  H04L47/10 ,  H04L47/16 ,  H04L47/263 ,  H04L47/30 ,  H04L2012/5635 ,  H04L2012/5651 ,  H04L2012/5682 ,  H04Q11/0478

摘要： A system includes a plurality of computers interconnected by a network including one or more switching nodes. The computers transfer messages over virtual circuits established thereamong. A computer, as a source computer for one or more virtual circuit(s), schedules transmission of messages on a round-robin basis as among the virtual circuits for which it is source computer. Each switching node which forms part of a path for respective virtual circuits also forwards messages for virtual circuits in a round-robin manner, and, a computer, as a destination computer for one or more virtual circuit(s), schedules processing of received messages in a round-robin manner. Round-robin transmission, forwarding and processing at the destination provides a degree of fairness in message transmission as among the virtual circuits established over the network. In addition, messages are transmitted in one or more cells, with the round-robin transmission being on a cell basis, so as to reduce delays which may occur for short messages if a long messages were transmitted in full for one virtual circuit before beginning transmission of a short message for another virtual circuit. For each virtual circuit, the destination computer and each switching node along the path for the virtual circuit can generate a virtual circuit flow control message for transmission to the source computer to temporarily limit transmission over the virtual circuit if the amount of resources being taken up by messages for the virtual circuit exceeds predetermined thresholds, further providing fairness as among the virtual circuits. In addition, each switching node or computer can generate link flow control messages for transmission to neighboring devices in the network to temporarily limit transmission thereto if the amount of resources taken up by all virtual circuits exceeds predetermined thresholds, so as to reduce the likelihood of message loss.

公开(公告)号：US6094712A

公开(公告)日：2000-07-25

申请号：US762186

申请日：1996-12-04

申请人： David R. Follett ,  Maria C. Gutierrez ,  Richard F. Prohaska

发明人： David R. Follett ,  Maria C. Gutierrez ,  Richard F. Prohaska

IPC分类号： G06F13/12 ,  G06F9/46 ,  G06F12/10 ,  G06F13/00 ,  H04L12/56 ,  H04Q11/04 ,  G06F12/00

CPC分类号： G06F9/546 ,  G06F12/1081 ,  H04Q11/0478 ,  H04L2012/5616 ,  H04L2012/5652 ,  H04L2012/5681

摘要： A computer interface system for communicating between computers along designated circuits is provided. An interface unit is provided in each host computer. Each unit includes a memory map that stores a map of physical addresses that correspond to virtual addresses for each application involved in a communication link. Each transfer of data is designated by a circuit that is established using the ATM protocol. The circuit is recognized by each unit involved in the communication and facilitates direct access of each host computer's main memory with minimum intervention from the operating system. A novel dynamic buffer management system is also provided.

摘要翻译： 提供了一种用于沿着指定电路在计算机之间进行通信的计算机接口系统。 在每个主机中提供接口单元。 每个单元包括存储映射，存储对应于通信链路中涉及的每个应用的虚拟地址的物理地址的映射。 每个数据传输由使用ATM协议建立的电路指定。 电路被通信中涉及的每个单元识别，并且可以通过操作系统的最小干预来促进每台主机的主存储器的直接访问。 还提供了一种新颖的动态缓冲管理系统。

公开(公告)号：US08214531B2

公开(公告)日：2012-07-03

申请号：US10280503

申请日：2002-10-24

申请人： Bino J. Sebastian ,  Richard F. Prohaska ,  James B. Williams

发明人： Bino J. Sebastian ,  Richard F. Prohaska ,  James B. Williams

IPC分类号： G06F15/16 ,  G06F11/00

CPC分类号： H04L41/0816 ,  H04L41/0856 ,  H04L69/10 ,  H04L69/12

摘要： Systems and techniques to synchronize network configuration for a hardware accelerated network protocol. According to an aspect, a network configuration record is maintained for a hardware-accelerated network-protocol device, a network configuration store is monitored to identify a network configuration change, and the hardware-accelerated network-protocol device is reconfigured, in response to the identified network configuration change, based on the network configuration record and the network configuration change.

摘要翻译： 用于硬件加速网络协议同步网络配置的系统和技术。 根据一方面，为硬件加速网络协议设备维护网络配置记录，监视网络配置存储以识别网络配置改变，并且响应于所述硬件加速网络协议设备重新配置硬件加速网络协议设备 识别网络配置更改，根据网络配置记录和网络配置更改。