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公开(公告)号：US07325024B2
公开(公告)日：2008-01-29
申请号：US10728127
申请日：2003-12-04
IPC分类号： G06F7/50
摘要： An adder circuit includes a number of selectors and an adder. The selectors feed the adder with multiple input data bits. Each of the selectors includes a combination of a multiplexing network and a sense amplifier to select from a number of input values to generate the multiple input data bits. The combination of the multiplexing network and the sense amplifier acts as the state-holding element at the input of the adder, avoiding the overheads of an explicit latch stage.
摘要翻译： 一个加法器电路包括多个选择器和一个加法器。 选择器为加法器提供多个输入数据位。 每个选择器包括复用网络和读出放大器的组合，以从多个输入值中选择以产生多个输入数据位。 复用网络和读出放大器的组合在加法器的输入端作为状态保持元件，避免显式锁存级的开销。
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公开(公告)号：US07840885B2
公开(公告)日：2010-11-23
申请号：US11860493
申请日：2007-09-24
IPC分类号： H03M13/41
CPC分类号： H03M13/6505 , H03M13/41 , H03M13/4169
摘要： Shift resister rings are used to provide column access in a traceback memory during Viterbi decoding.
摘要翻译： 移位电阻环用于在维特比解码期间在追溯存储器中提供列访问。
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公开(公告)号：US06628143B2
公开(公告)日：2003-09-30
申请号：US09965360
申请日：2001-09-26
IPC分类号： H03K19096
CPC分类号： H03K19/0963
摘要： An embodiment of a full-swing, source-follower leakage tolerant dynamic logic gate comprises an nMOSFET logic to conditionally charge a node during an evaluation phase, and to charge the node to a relatively small voltage during the pre-charge phase so that the nMOSFET logic becomes reverse-biased.
摘要翻译： 全驱动，源极跟随器泄漏容限动态逻辑门的实施例包括nMOSFET逻辑，用于在评估阶段对节点进行有条件充电，并且在预充电阶段期间将节点充电至相对小的电压，使得nMOSFET 逻辑变为反向偏置。
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公开(公告)号：US07380099B2
公开(公告)日：2008-05-27
申请号：US10956164
申请日：2004-09-30
IPC分类号： G06F12/00
摘要： A method and apparatus for an address generation circuit. In one embodiment, the method includes computing a carry-in for at least one group of a predetermined number of bits of a propagate and a generate signal formed from a plurality of logical address components. Once the carry-in is computed, a plurality of conditional sums are generated for a logic 0 carry-in and a logic 1 carry-in. Subsequently, a sum is selected from the plurality of conditional sums to form a first portion of an effective address from the logical address components in a first stage and a second portion of the effective address in a second stage. In one embodiment, a fully dynamic high-performance sparse tree adder circuit that generates one in four carries, is used to form an address generation circuit, in accordance with one embodiment. Other embodiments are described and claimed.
摘要翻译： 一种用于地址产生电路的方法和装置。 在一个实施例中，该方法包括计算由多个逻辑地址分量形成的传播信号和生成信号的预定位数的至少一组的进位。 一旦计算了进位，则为逻辑0进位和逻辑1进位产生多个条件和。 随后，从多个条件和中选出一个和，以在第二阶段中的第一阶段的逻辑地址分量和有效地址的第二部分中形成有效地址的第一部分。 在一个实施例中，根据一个实施例，使用产生四分之一载波的完全动态的高性能稀疏树加法器电路来形成地址生成电路。 描述和要求保护其他实施例。
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公开(公告)号：US20150280909A1
公开(公告)日：2015-10-01
申请号：US14227718
申请日：2014-03-27
申请人： Sanu K. Mathew , Himanshu Kaul , Mark A. Anders
发明人： Sanu K. Mathew , Himanshu Kaul , Mark A. Anders
CPC分类号： H04L9/0618 , G06F21/62 , G09C1/00 , H04L2209/24
摘要： A processor includes an input-circuit and a Simon block cipher. The Simon block cipher includes a data transformation circuit, a constant generator, and a key expansion circuit. The data transformation circuit includes logic to shift content of data storage registers. The key expansion circuit includes logic to determine a round key based upon an input symmetric key and data input, a previous round key, and a value from the constant generator. The constant generator includes logic to output a successive one of a list of constants each clock cycle, and to store the outputted constants in storage units. The number of storage units is less than the size of the list of constants.
摘要翻译： 处理器包括输入电路和西门子分组密码。 Simon分组密码包括数据变换电路，恒定发生器和密钥扩展电路。 数据变换电路包括移位数据存储寄存器的内容的逻辑。 密钥扩展电路包括基于输入对称密钥和数据输入，先前的循环密钥和来自常量发生器的值来确定循环密钥的逻辑。 常数发生器包括用于输出每个时钟周期的常数列表中的连续的一个的逻辑，并将输出的常数存储在存储单元中。 存储单元的数量小于常量列表的大小。
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公开(公告)号：US07509368B2
公开(公告)日：2009-03-24
申请号：US11123702
申请日：2005-05-09
IPC分类号： G06F7/50
摘要： An adder circuit is provided that includes a propagate and generate circuit stage to provide propagate and generate signals, a plurality of carry-merge stages to provide carry signals based on the propagate and generate signals and a conditional sum generator to provide conditional sums based on the propagate and generate signals. The conditional sum generator includes ripple carry gates and XOR logic gates. The adder circuit also includes a plurality of multiplexers to receive the carry signals and the conditional sums and to provide an output based on the input signals.
摘要翻译： 提供了一种加法器电路，其包括传播和产生电路级以提供传播和产生信号;多个进位合并级，用于基于传播和产生信号提供进位信号;以及条件和发生器，以基于 传播和产生信号。 条件和生成器包括纹波进位门和异或逻辑门。 加法器电路还包括多个多路复用器，用于接收进位信号和条件和，并且基于输入信号提供输出。
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公开(公告)号：US09473296B2
公开(公告)日：2016-10-18
申请号：US14227718
申请日：2014-03-27
申请人： Sanu K. Mathew , Himanshu Kaul , Mark A. Anders
发明人： Sanu K. Mathew , Himanshu Kaul , Mark A. Anders
CPC分类号： H04L9/0618 , G06F21/62 , G09C1/00 , H04L2209/24
摘要： A processor includes an input-circuit and a Simon block cipher. The Simon block cipher includes a data transformation circuit, a constant generator, and a key expansion circuit. The data transformation circuit includes logic to shift content of data storage registers. The key expansion circuit includes logic to determine a round key based upon an input symmetric key and data input, a previous round key, and a value from the constant generator. The constant generator includes logic to output a successive one of a list of constants each clock cycle, and to store the outputted constants in storage units. The number of storage units is less than the size of the list of constants.
摘要翻译： 处理器包括输入电路和西门子分组密码。 Simon分组密码包括数据变换电路，恒定发生器和密钥扩展电路。 数据变换电路包括移位数据存储寄存器的内容的逻辑。 密钥扩展电路包括基于输入对称密钥和数据输入，先前的循环密钥和来自常量发生器的值来确定循环密钥的逻辑。 常数发生器包括用于输出每个时钟周期的常数列表中的连续的一个的逻辑，并将输出的常数存储在存储单元中。 存储单元的数量小于常量列表的大小。
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公开(公告)号：US06828841B2
公开(公告)日：2004-12-07
申请号：US10652668
申请日：2003-08-29
IPC分类号： H03F345
CPC分类号： G06F1/10
摘要： A clock receiver circuit converts low amplitude, differential clock signal components received from a differential clock distribution medium into a full swing digital clock. The clock receiver circuit can be used as part of, for example, an on-die salphasic clock distribution system within a microelectronic device.
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公开(公告)号：US06225826B1
公开(公告)日：2001-05-01
申请号：US09220816
申请日：1998-12-23
IPC分类号： H03K19096
CPC分类号： H03K19/096 , H03K19/0963
摘要： In some embodiments, the invention includes a domino logic gate circuit having a domino state and a single ended domino compatible dual function generator. The domino state receives a domino stage input signal and provides a single ended intermediate signal as a function of the domino stage input signal, the intermediate signal having a state. The generator receives the intermediate signal and provides an out signal and an out* signal each having a state, wherein the out and out* signals have the same state during a precharge phase and have complementary states during an evaluate phase as a function of the state of the intermediate signal. In other embodiments, the invention includes domino logic gate circuit having a combined domino stage and dual function generator. The domino stage is to receive a domino stage input signal. The dual function generator is a single ended domino compatible dual function generator to provide an out signal and an out* signal that each have a state and during a precharge phase, the out signal and out* signal each have the same state, and during an evaluate phase the out and out* states are complementary states as a function of the domino stage input signal without a logic X circuit and a logic X* circuit.
摘要翻译： 在一些实施例中，本发明包括具有多米诺骨架状态和单端多米诺骨牌兼容双功能发生器的多米诺逻辑门电路。 多米诺骨牌状态接收多米诺骨牌级输入信号，并提供作为多米诺骨牌级输入信号的函数的单端中间信号，中间信号具有状态。 发生器接收中间信号并提供各自具有状态的输出信号和输出信号，其中输出和输出信号在预充电阶段期间具有相同的状态，并且在作为状态的函数的评估阶段期间具有互补状态 的中间信号。 在其他实施例中，本发明包括具有组合多米诺舞台和双功能发生器的多米诺逻辑门电路。 多米诺骨牌阶段是接收多米诺骨牌阶段的输入信号。 双功能发生器是单端多米诺骨牌兼容双功能发生器，用于提供每个具有状态的输出信号和输出信号，并且在预充电阶段期间，输出信号和输出信号各自具有相同的状态，并且在 评估相位，out和out *状态是互补状态，作为多米诺舞台输入信号的函数，没有逻辑X电路和逻辑X *电路。
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10.发明申请ARCHITECTURE AND METHOD FOR HYBRID CIRCUIT-SWITCHED AND PACKET-SWITCHED ROUTER 有权用于混合电路切换和分组交换路由器的架构和方法公开(公告)号：US20150071282A1
公开(公告)日：2015-03-12
申请号：US14129544
申请日：2013-09-06
IPC分类号： H04L12/64
CPC分类号： H04L12/6418 , G06F15/7825 , H04L49/109 , H04L49/251 , H04L49/252 , H04L49/9042
摘要： Techniques and mechanisms for performing circuit-switched routing and packet-switched routing for network communication. In an embodiment, a router evaluates control information of a packet received by the router, the evaluation to detect whether the packet includes data for a sideband communication. Based on the evaluation, the router performs a selection from among a plurality of modes of the router, the plurality of modes including a first mode to route the packet for packet-switched communication of sideband data in a network. The plurality of modes also includes a second mode to configure a circuit-switched channel according to the packet. In another embodiment, the router determines a direction for routing a packet in a hierarchical network, wherein the determining of the direction is based on a level of the router in a hierarchy of the hierarchical network.
摘要翻译： 用于执行电路交换路由和分组交换路由以用于网络通信的技术和机制。 在一个实施例中，路由器评估由路由器接收的分组的控制信息，评估以检测分组是否包括用于边带通信的数据。 基于该评估，路由器从路由器的多个模式中进行选择，该多个模式包括在网络中路由用于边带数据的分组交换通信的分组的第一模式。 多个模式还包括根据分组配置电路交换信道的第二模式。 在另一个实施例中，路由器确定用于在分层网络中路由分组的方向，其中所述方向的确定基于所述分级网络的层级中的路由器的级别。
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