公开(公告)号：US07360117B1

公开(公告)日：2008-04-15

申请号：US10279344

申请日：2002-10-24

申请人： Mark A. Boike ,  Alan Phan ,  Brendon J. Slade

发明人： Mark A. Boike ,  Alan Phan ,  Brendon J. Slade

IPC分类号： G06F11/00

CPC分类号： G06F11/3652

摘要： An in-circuit emulation debugger and method of operating an in-circuit emulation debugger to test a digital signal processor (DSP). In one embodiment, the in-circuit emulation debugger includes: (1) a device emulation unit, coupled to a collocated DSP core, for emulating circuitry that is to interact with the DSP core, (2) an external processor interface, coupled to the device emulation unit, that receives control signals from an external processor that cause the device emulation unit to provide a test environment for the DSP core and (3) a breakpoint detection circuit, associated with the device emulation unit, that responds to preprogrammed breakpoints based on occurrences of events both internal and external to the DSP core.

摘要翻译： 一种在线仿真调试器和操作在线仿真调试器来测试数字信号处理器（DSP）的方法。 在一个实施例中，在线仿真调试器包括：（1）耦合到并置的DSP核的器件仿真单元，用于仿真与DSP内核交互的电路;（2）外部处理器接口，耦合到 设备仿真单元，其接收来自外部处理器的控制信号，所述控制信号使得所述设备仿真单元为所述DSP内核提供测试环境;以及（3）与所述设备仿真单元相关联的断点检测电路，所述断点检测电路基于预编程的断点， 事件发生在DSP核心的内部和外部。

公开(公告)号：US06845412B1

公开(公告)日：2005-01-18

申请号：US10045889

申请日：2001-11-07

申请人： Mark A. Boike ,  Alan Phan

发明人： Mark A. Boike ,  Alan Phan

IPC分类号： G06F3/00 ,  G06F13/16

CPC分类号： G06F13/1652

摘要： A system and method are presented for an external host processor to distribute data to memory devices associated with multiple digital signal processors (DSPs) within an integrated circuit “system on a chip.” A host processor interface in the multi-processor integrated circuit responds to commands from the host processor and provides access to the memory devices. A control register in the interface is directly accessible by the host processor, and is used to generate various control signals in response to host processor commands. A data control register in the interface has a field of write enable bits that directly control write accessibility of the memory devices—if a designated write-enable bit within the data control register is set, the corresponding memory devices are write enabled. An extended address bit in the control register is used to select either instruction or data memory for write access.

摘要翻译： 提出了一种用于外部主机处理器将数据分配到与集成电路“芯片上的系统”中的多个数字信号处理器（DSP）相关联的存储器件的系统和方法。 多处理器集成电路中的主机处理器接口响应来自主处理器的命令，并提供对存储器件的访问。 接口中的控制寄存器可由主处理器直接访问，并用于响应于主机处理器命令生成各种控制信号。 接口中的数据控制寄存器具有直接控制存储器件写入可访问性的写使能位的字段 - 如果数据控制寄存器中指定的写使能位被置位，则相应的存储器件被写使能。 控制寄存器中的扩展地址位用于选择任一指令或数据存储器进行写访问。

公开(公告)号：US06715038B1

公开(公告)日：2004-03-30

申请号：US09993431

申请日：2001-11-05

申请人： Hung T. Nguyen ,  Mark A. Boike

发明人： Hung T. Nguyen ,  Mark A. Boike

IPC分类号： G06F1300

CPC分类号： G06F12/08 ,  G06F12/0875 ,  G06F12/0891

摘要： For use in a processor having an instruction cache, an instruction memory and an external synchronous memory, a memory management mechanism, a method of managing memory and a digital signal processor incorporating the mechanism or the method. In one embodiment, the mechanism includes an external memory request abort circuit coupled to the external synchronous memory and an instruction cache invalidator associated with the external memory request abort circuit. In this embodiment, the external memory request abort circuit aborts a request to load an instruction from the external synchronous memory before the information is loaded into the instruction cache. Additionally, the instruction cache invalidator invalidates the instruction cache when address spaces of the instruction memory and the external synchronous memory overlap and the processor switches between the instruction memory and the external synchronous memory.

摘要翻译： 用于具有指令高速缓存，指令存储器和外部同步存储器的处理器，存储器管理机制，管理存储器的方法和结合该机构或方法的数字信号处理器。 在一个实施例中，该机制包括耦合到外部同步存储器的外部存储器请求中止电路和与外部存储器请求中止电路相关联的指令高速缓存无效器。 在本实施例中，在将信息加载到指令高速缓存器之前，外部存储器请求中止电路中止从外部同步存储器加载指令的请求。 此外，当指令存储器和外部同步存储器的地址空间重叠并且处理器在指令存储器和外部同步存储器之间切换时，指令高速缓存无效器使指令高速缓存失效。