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公开(公告)号:US06449694B1
公开(公告)日:2002-09-10
申请号:US09362919
申请日:1999-07-27
IPC分类号: G06F1200
CPC分类号: G06F12/0864 , G06F2212/1028 , Y02D10/13
摘要: A method for conserving power during a cache memory operation is disclosed. The validity and the parity of the tag address are checked. If the tag is invalid or the parity bit does not check, the tag is not read and a tag comparison is not performed, such that the data is accessed from the main memory. Otherwise, the tag address bits are selected in a plurality of tag subsets. A first tag subset of the plurality of tag subsets is compared with a respective first subset of the tag field of the memory address bits. A first compare signal indicative of the result of the first comparison is outputted. The cache memory operation is interrupted if the first compare signal indicates the first tag subset does not match the respective first subset of the tag field of the memory address.
摘要翻译: 公开了一种用于在高速缓存存储器操作期间节省功率的方法。 检查标签地址的有效性和奇偶校验。 如果标签无效或奇偶校验位未检查,则不读取标签并且不执行标签比较,使得从主存储器访问数据。 否则,在多个标签子集中选择标签地址位。 将多个标签子集中的第一标签子集与存储器地址位的标签字段的相应第一子集进行比较。 输出表示第一比较结果的第一比较信号。 如果第一比较信号指示第一标签子集与存储器地址的标签字段的相应第一子集不匹配,则高速缓存存储器操作被中断。
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公开(公告)号:US06434736B1
公开(公告)日:2002-08-13
申请号:US09351100
申请日:1999-07-08
IPC分类号: G11C1100
摘要: A method and apparatus for improving the access time of a memory device is described. The location based timing scheme utilizes a subset of the address bits to adjust the timing of the sense amplifier enable in order to achieve a faster read of the information stored in the memory cell.
摘要翻译: 描述了一种用于改善存储器件的访问时间的方法和装置。 基于位置的定时方案利用地址位的子集来调整读出放大器使能的定时,以便更快地读取存储在存储单元中的信息。
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公开(公告)号:US06608779B1
公开(公告)日:2003-08-19
申请号:US09587495
申请日:2000-06-02
IPC分类号: G11C700
CPC分类号: G11C7/1006 , G06F9/30141 , G06F9/30189
摘要: Embodiments are disclosed that include a low power memory and/or a low power data path. One particular embodiment, for example, includes a technique to reduce power consumption. In one particular embodiment, for example, a grouping of bits, such as a 32-bit word, for example, is stored in inverted form if more than half of the bits have a bit value of logic “1” rather than logic “0.” Likewise, in this embodiment, if more than half of the bits have a bit value of logic “0” rather than logic “1,” then the grouping of bits is not stored in inverted form.
摘要翻译: 公开了包括低功率存储器和/或低功率数据路径的实施例。 例如,一个具体实施例包括减少功耗的技术。 在一个特定实施例中,例如,如果多于一半的比特具有逻辑“1”的比特值而不是逻辑“0”,则比特的诸如32比特字的分组以反向形式被存储 “。 同样,在本实施例中,如果多于一半的比特具有逻辑“0”的比特值而不是逻辑“1”,则比特的分组不以倒置形式存储。
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公开(公告)号:US06690607B2
公开(公告)日:2004-02-10
申请号:US10368969
申请日:2003-02-18
IPC分类号: G11C700
CPC分类号: G11C7/1006 , G06F9/30141 , G06F9/30189
摘要: Embodiments of the invention are disclosed that include a low power memory and a low power data path.
摘要翻译: 公开了包括低功率存储器和低功率数据路径的本发明的实施例。
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