公开(公告)号：US06552949B1

公开(公告)日：2003-04-22

申请号：US10062567

申请日：2002-02-05

申请人： Mark Allen Silla ,  Arthur R Piejko ,  Michael Louis Brauer ,  Gerard Richard Williams, III

发明人： Mark Allen Silla ,  Arthur R Piejko ,  Michael Louis Brauer ,  Gerard Richard Williams, III

IPC分类号： G11C700

CPC分类号： G11C11/417 ,  G11C7/1048 ,  G11C7/12 ,  G11C7/20 ,  G11C11/419 ,  G11C2207/2227

摘要： The present invention relates to a memory device and method for reducing leakage current during a power down mode of operation. The memory device comprises a column of memory cells, with each memory cell being arranged to store a data value, and a pair of bit lines coupled to the column of memory cells. Bit line precharge circuitry is provided for precharging the pair of bit lines to a predetermined voltage level during a precharge phase, the pair of bit lines being arranged such that, when a particular memory cell in the column is selected in an evaluate phase following the precharge phase, a relative change in voltage level between the pair of bit lines indicates the data value stored within the selected memory cell. In accordance with the present invention, the memory device further comprises power down control circuitry arranged when the memory device is to enter a power down mode to prevent the bit line precharge circuitry from precharging the pair of bit lines, and selector circuitry arranged when the memory device is to enter the power down mode to ensure that none of the memory cells in the column are selected. It has been found that by taking this approach during the power down mode of operation, a significant reduction in the leakage current is observed.

摘要翻译： 本发明涉及一种用于在掉电操作模式期间减少泄漏电流的存储器件和方法。 存储器件包括一列存储器单元，每个存储器单元被布置成存储数据值，以及耦合到存储器单元列的一对位线。 位线预充电电路被提供用于在预充电阶段期间将一对位线预充电到预定电压电平，该位位线布置成使得当在预充电之后的评估阶段选择列中的特定存储单元时 一对位线之间的电压电平的相对变化指示存储在所选存储单元内的数据值。 根据本发明，存储器件还包括掉电控制电路，当存储器件要进入掉电模式时被布置，以防止位线预充电电路对该对位线进行预充电;以及选择器电路，当存储器 设备进入掉电模式，以确保列中没有一个存储单元被选中。 已经发现，通过在断电操作模式期间采取该方法，可以观察到泄漏电流的显着降低。