公开(公告)号：US20060044011A1

公开(公告)日：2006-03-02

申请号：US10930091

申请日：2004-08-31

申请人： Mark Andresen ,  Robert Christopher ,  James Parsonese ,  William Thomas ,  Wilson Velez ,  David Vieira ,  Menlo Wuu

发明人： Mark Andresen ,  Robert Christopher ,  James Parsonese ,  William Thomas ,  Wilson Velez ,  David Vieira ,  Menlo Wuu

IPC分类号： H03K19/0175

CPC分类号： H03K19/01843

摘要： A bi-directional voltage translator is disclosed. The bi-directional voltage translator includes a step-up voltage translator for converting signals of a first voltage level to signals of a second voltage level, and a step-down voltage translator for converting signals of the second voltage level to signals of the first voltage level. The step-up voltage translator includes a first source sense circuit, a first block feedback circuit and a first output driver circuit. The step-down voltage translator includes a second source sense circuit, a second block feedback circuit and a second output driver circuit.

摘要翻译： 公开了一种双向电压转换器。 双向电压转换器包括升压电压转换器，用于将第一电压电平的信号转换成第二电压电平的信号;以及降压电压转换器，用于将第二电压电平的信号转换成第一电压的信号 水平。 升压电压转换器包括第一源检测电路，第一块反馈电路和第一输出驱动器电路。 降压电压转换器包括第二源检测电路，第二块反馈电路和第二输出驱动器电路。

公开(公告)号：US07936223B2

公开(公告)日：2011-05-03

申请号：US12284924

申请日：2008-09-25

申请人： James M. Little ,  Perry Leigh Heedley ,  David Vieira ,  Maoyou Sun

发明人： James M. Little ,  Perry Leigh Heedley ,  David Vieira ,  Maoyou Sun

IPC分类号： H03L7/00

CPC分类号： H04L47/6245 ,  G06F1/10 ,  H03L7/00 ,  H04B3/32 ,  H04J3/0697 ,  H04L25/0278 ,  H04L43/16 ,  H04L47/25 ,  H04L47/521 ,  H04L47/6215 ,  H04L47/722

摘要： A low spur phase-locked loop (PLL) architecture is provided. A frequency-synthesizing PLL that includes a differential Kvco gain linearization circuit with adjustable DC offset is used to reduce clock jitter. The free-running oscillation frequency of the VCO of the PLL is centered near the desired frequency using programmable loads to minimize the required control voltage range. The PLL uses a differential architecture that includes a charge pump that compensates for variations in Kvco and a LC tank oscillator with differential controlled varactor. The differential PLL architecture demonstrates that the reference spur can be well controlled to below −80 dBc.

摘要翻译： 提供了低支路锁相环（PLL）架构。 包括具有可调DC偏移的差分Kvco增益线性化电路的频率合成PLL被用于减少时钟抖动。 使用可编程负载，PLL的VCO的自由振荡频率居中在所需频率附近，以最小化所需的控制电压范围。 PLL使用差分架构，其包括电荷泵，其补偿Kvco和具有差动控制变容二极管的LC振荡器的变化。 差分PLL结构表明，参考杂散可以很好地控制在-80 dBc以下。

公开(公告)号：US20090231046A1

公开(公告)日：2009-09-17

申请号：US12284924

申请日：2008-09-25

申请人： James M. Little ,  Perry Leigh Heedley ,  David Vieira ,  Maoyou Sun

发明人： James M. Little ,  Perry Leigh Heedley ,  David Vieira ,  Maoyou Sun

IPC分类号： H03L7/00

CPC分类号： H04L47/6245 ,  G06F1/10 ,  H03L7/00 ,  H04B3/32 ,  H04J3/0697 ,  H04L25/0278 ,  H04L43/16 ,  H04L47/25 ,  H04L47/521 ,  H04L47/6215 ,  H04L47/722

摘要： A low spur phase-locked loop (PLL) architecture is provided. A frequency-synthesizing PLL that includes a differential Kvco gain linearization circuit with adjustable DC offset is used to reduce clock jitter. The free-running oscillation frequency of the VCO of the PLL is centered near the desired frequency using programmable loads to minimize the required control voltage range. The PLL uses a differential architecture that includes a charge pump that compensates for variations in Kvco and a LC tank oscillator with differential controlled varactor. The differential PLL architecture demonstrates that the reference spur can be well controlled to below −80 dBc.

摘要翻译： 提供了低支路锁相环（PLL）架构。 包括具有可调DC偏移的差分Kvco增益线性化电路的频率合成PLL被用于减少时钟抖动。 使用可编程负载，PLL的VCO的自由振荡频率居中在所需频率附近，以最小化所需的控制电压范围。 PLL使用差分架构，其包括电荷泵，其补偿Kvco和具有差动控制变容二极管的LC振荡器的变化。 差分PLL结构表明，参考杂散可以很好地控制在-80 dBc以下。