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1.发明授权Computer method and apparatus for division and square root operations using signed digit 有权使用有符号数字的分割和平方根操作的计算机方法和装置公开(公告)号：US06779012B2
公开(公告)日：2004-08-17
申请号：US10419454
申请日：2003-04-18
IPC分类号： G06F7552
CPC分类号： G06F7/535 , G06F7/4824 , G06F7/508 , G06F7/5525 , G06F9/3814 , G06F9/3838 , G06F9/384 , G06F2207/5352
摘要： Computer method and apparatus for performing a square root or division operation generating a root or quotient. A partial remainder is stored in radix-2 or radix-4 signed digit format. A decoder is provided for computing a root or quotient digit, and a correction term dependent on a number of the most significant digits of the partial remainder. An adder is provided for computing the sum of the signed digit partial remainder and the correction term in binary format, and providing the result in signed digit format. The adder computes a carry out independent of a carry in bit and a sum dependent on a Carry_in bit providing a fast adder independent of carry propagate delays. The scaler performs a multiplication by two of the result output from the adder in signed digit format to provide a signed digit next partial remainder.
摘要翻译： 用于执行产生根或商的平方根或除法运算的计算机方法和装置。 部分余数以radix-2或radix-4有符号数字格式存储。 提供用于计算根数或商数的解码器，以及取决于部分余数的最高有效数字的数量的校正项。 提供加法器，用于计算二进制格式的有符号位部分余数和校正项的和，并以带符号数字格式提供结果。 加法器计算独立于比特进位的进位和取决于提供独立于进位传播延迟的快速加法器的Carry_in位的和。 缩放器执行乘法运算结果从加法器输出的两个符号数字格式，以提供一个有符号数字的下一个部分余数。
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2.发明授权Computer method and apparatus for division and square root operations using signed digit 有权使用有符号数字的分割和平方根操作的计算机方法和装置公开(公告)号：US06360241B1
公开(公告)日：2002-03-19
申请号：US09294597
申请日：1999-04-20
IPC分类号： B06F700
CPC分类号： G06F7/535 , G06F7/4824 , G06F7/508 , G06F7/5525 , G06F9/3814 , G06F9/3838 , G06F9/384 , G06F2207/5352
摘要： The invention provides computer apparatus for performing a square root or division operation generating a root or quotient. A partial remainder is stored in radix-2 or radix-4 signed digit format. A decoder is provided for computing a root or quotient digit, and a correction term dependent on a number of the most significant digits of the partial remainder. An adder is provided for computing the sum of the signed digit partial remainder and the correction term in binary format, and providing the result in signed digit format. The adder computes a carry out independent of a carry in bit and a sum dependent on a Carry_in bit providing a fast adder independent of carry propagate delays. The scaler performs a multiplication by two of the result output from the adder in signed digit format to provide a signed digit next partial remainder.
摘要翻译： 本发明提供用于执行产生根或商的平方根或除法运算的计算机装置。 部分余数以radix-2或radix-4有符号数字格式存储。 提供用于计算根数或商数的解码器，以及取决于部分余数的最高有效数字的数量的校正项。 提供加法器，用于计算二进制格式的有符号位部分余数和校正项的和，并以带符号数字格式提供结果。 加法器计算独立于比特进位的进位和取决于提供独立于进位传播延迟的快速加法器的Carry_in位的和。 缩放器执行乘法运算结果从加法器输出的两个符号数字格式，以提供一个有符号数字的下一个部分余数。
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公开(公告)号：US6144228A
公开(公告)日：2000-11-07
申请号：US340774
申请日：1999-06-28
IPC分类号： G06F7/48 , G06F7/50 , G06F7/52 , G06F7/535 , H03K19/0948
CPC分类号： G06F7/535 , G06F7/4824 , G06F7/508 , G06F9/3814 , G06F9/3838 , G06F9/384 , G06F2207/5352
摘要： A method and apparatus are presented for efficient implementation of logic and arithmetic functions that generate sets of mutually exclusive output signals. Such a logic family includes a network of NMOS transistors that implements a desired logic function. Coupled to that network is a minimal number of PMOS devices for providing logic level restoration and for compensating for any voltage drops due to the NMOS transistors. With such a structure, the speed, area and power consumption characteristics of logic functions are improved.
摘要翻译： 提出了一种方法和装置，用于有效地实现产生一组相互排斥的输出信号的逻辑和算术功能。 这种逻辑系列包括实现所需逻辑功能的NMOS晶体管网络。 耦合到该网络是用于提供逻辑电平恢复并用于补偿由于NMOS晶体管的任何电压降的最小数量的PMOS器件。 通过这样的结构，提高了逻辑功能的速度，面积和功耗特性。
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4.发明授权Computer method and apparatus for division and square root operations using signed digit 有权使用有符号数字的分割和平方根操作的计算机方法和装置公开(公告)号：US06564239B2
公开(公告)日：2003-05-13
申请号：US10016902
申请日：2001-12-14
IPC分类号： G06F738
CPC分类号： G06F7/535 , G06F7/4824 , G06F7/508 , G06F7/5525 , G06F9/3814 , G06F9/3838 , G06F9/384 , G06F2207/5352
摘要： Computer method and apparatus for performing a square root or division operation generating a root or quotient is presented. A partial remainder is stored in radix-2 or radix-4 signed digit format. A decoder is provided for computing a root or quotient digit, and a correction term dependent on a number of the most significant digits of the partial remainder. An adder is provided for computing the sum of the signed digit partial remainder and the correction term in binary format, and providing the result in signed digit format. The adder computes a carry out independent of a carry in bit and a sum dependent on a Carry_in bit providing a fast adder independent of carry propagate delays. The scaler performs a multiplication by two of the result output from the adder in signed digit format to provide a signed digit next partial remainder.
摘要翻译： 呈现用于执行产生根或商的平方根或除法运算的计算机方法和装置。 部分余数以radix-2或radix-4有符号数字格式存储。 提供用于计算根数或商数的解码器，以及取决于部分余数的最高有效数字的数量的校正项。 提供加法器，用于计算二进制格式的有符号位部分余数和校正项的和，并以带符号数字格式提供结果。 加法器计算独立于比特进位的进位和取决于提供独立于进位传播延迟的快速加法器的Carry_in位的和。 缩放器执行乘法运算结果从加法器输出的两个符号数字格式，以提供一个有符号数字的下一个部分余数。
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公开(公告)号：US06653869B2
公开(公告)日：2003-11-25
申请号：US10077194
申请日：2002-02-15
IPC分类号： G01R1900
CPC分类号： G01R19/0084
摘要： A sense amplifier is provided for sensing an input voltage level of a data signal. Such a sense amplifier pre-charges, and subsequently discharges, a pair of nodes through a respective pair of discharge paths. Each of those discharge paths is capable of performing the discharge operation at a rate that is related to either a system voltage supply or an input logic level of the data signal. Because the discharge path that is associated with the data signal includes a greater amount of conductance, it can perform the discharge operation at a faster rate, even where the input logic level does not exceed the voltage of the system voltage supply. A determination is made as to which of the discharge is the faster and, responsively, a rail-to-rail output signal having the same polarity as the data signal, is generated. The input data signal is conveyed to the sense amplifier by a single wire. Also, the sense amplifier does not require a specialized reference voltage for proper operation. Rather, it uses the same voltage supply that is used to power the rest of the circuit. Accordingly, such an approach uses less area, consumes less power and has greater noise immunity.
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6.发明授权Universal CMOS single input, low swing sense amplifier without reference voltage 失效通用CMOS单输入，低摆幅读出放大器无参考电压公开(公告)号：US06414520B1
公开(公告)日：2002-07-02
申请号：US09241496
申请日：1999-02-01
IPC分类号： G01R1900
CPC分类号： G01R19/0084
摘要： A sense amplifier for sensing an input voltage level of a data signal. Such a sense amplifier pre-charges, and subsequently discharges, a pair of nodes through a respective pair of discharge paths. Each of those discharge paths is capable of performing the discharge operation at a rate that is related to either a system voltage supply or an input logic level of the data signal. Because the discharge path that is associated with the data signal includes a greater amount of conductance, it can perform the discharge operation at a faster rate, even where the input logic level does not exceed the voltage of the system voltage supply. A determination is made as to which of the discharge is the faster and, responsively, a rail-to-rail output signal having the same polarity as the data signal, is generated.
摘要翻译： 用于感测数据信号的输入电压电平的读出放大器。 这种感测放大器预先对一对节点通过相应的一对放电路径进行预充电并随后放电。 这些放电路径中的每一个能够以与系统电压供应或数据信号的输入逻辑电平相关的速率执行放电操作。 由于与数据信号相关联的放电路径包括较大的电导量，所以即使在输入逻辑电平不超过系统电压电压的电压的情况下，也可以以更快的速率执行放电操作。 确定放电的哪一个更快，并且响应地产生具有与数据信号相同的极性的轨到轨输出信号。
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公开(公告)号：US07868706B2
公开(公告)日：2011-01-11
申请号：US12256736
申请日：2008-10-23
申请人： Arshad I. Nissar , Jan-Michael Huber , Brian M. Lay , Kshitij Seth , Keith Burwinkel , Robert J. Dupcak
发明人： Arshad I. Nissar , Jan-Michael Huber , Brian M. Lay , Kshitij Seth , Keith Burwinkel , Robert J. Dupcak
CPC分类号： H03K3/0315
摘要： An oscillator device includes a plurality of stages. Each stage is a monostable stage having a delay path, whereby a signal transition of a designated type (rising or falling) at the input of the delay path results in a signal transition at the output of the stage of the same transition type. Each stage of the oscillator device also includes a reset module that causes the output signal to be reset to a nominal state a predetermined period of time after the signal transition of the output signal. Each stage thus provides an output signal pulse in response to the signal transition of the designated type at the input. The output of the final stage of the oscillator device is connected to the input, so that the oscillator output provides an oscillating signal having a period based upon the delay path of each the oscillator device stages.
摘要翻译： 振荡器装置包括多个级。 每个级是具有延迟路径的单稳态级，由此在延迟路径的输入处的指定类型（上升或下降）的信号转换导致在相同转换类型的级的输出处的信号转换。 振荡器装置的每一级还包括复位模块，该复位模块在输出信号的信号转换之后的预定时间段内将输出信号复位到标称状态。 因此，每个级都响应于输入处的指定类型的信号转换而提供输出信号脉冲。 振荡器装置的最后级的输出连接到输入端，使得振荡器输出提供具有基于每个振荡器装置级的延迟路径的周期的振荡信号。
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公开(公告)号：US20100102891A1
公开(公告)日：2010-04-29
申请号：US12256736
申请日：2008-10-23
申请人： Arshad I. Nissar , Jan-Michael Huber , Brian M. Lay , Kshitij Seth , Keith Burwinkel , Robert J. Dupcak
发明人： Arshad I. Nissar , Jan-Michael Huber , Brian M. Lay , Kshitij Seth , Keith Burwinkel , Robert J. Dupcak
IPC分类号： H03K3/03
CPC分类号： H03K3/0315
摘要： An oscillator device includes a plurality of stages. Each stage is a monostable stage having a delay path, whereby a signal transition of a designated type (rising or falling) at the input of the delay path results in a signal transition at the output of the stage of the same transition type. Each stage of the oscillator device also includes a reset module that causes the output signal to be reset to a nominal state a predetermined period of time after the signal transition of the output signal. Each stage thus provides an output signal pulse in response to the signal transition of the designated type at the input. The output of the final stage of the oscillator device is connected to the input, so that the oscillator output provides an oscillating signal having a period based upon the delay path of each the oscillator device stages.
摘要翻译： 振荡器装置包括多个级。 每个级是具有延迟路径的单稳态级，由此在延迟路径的输入处的指定类型（上升或下降）的信号转换导致在相同转换类型的级的输出处的信号转换。 振荡器装置的每一级还包括复位模块，该复位模块在输出信号的信号转换之后的预定时间段内将输出信号复位到标称状态。 因此，每个级都响应于输入处的指定类型的信号转换而提供输出信号脉冲。 振荡器装置的最后级的输出连接到输入端，使得振荡器输出提供具有基于每个振荡器装置级的延迟路径的周期的振荡信号。
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