公开(公告)号：US5606562A

公开(公告)日：1997-02-25

申请号：US682484

申请日：1996-07-17

Applicant: Mark Landguth

Inventor： Mark Landguth

IPC: H04J3/16 ,  H04L1/00 ,  H04L12/64 ,  H04J3/07

CPC classification number: H04L1/0068 ,  H04J3/1647 ,  H04L12/64 ,  H04L12/6418 ,  H04L2012/6427 ,  H04L2012/6454 ,  H04L2012/6459 ,  H04Q2213/13103 ,  H04Q2213/13106 ,  H04Q2213/13214 ,  H04Q2213/1322 ,  H04Q2213/13292 ,  H04Q2213/13299 ,  H04Q2213/1336 ,  H04Q2213/13389

Abstract: A first station is connectable to a second station for transmitting a predetermined fixed amount of data to the second station over a predetermined time period to achieve a predetermined fixed data transmission rate. The predetermined time period consists of a plurality of constituent time periods. An amount of substantive data, which is less than the predetermined fixed amount of data, is transmitted from the first station to the second station in the predetermined time period by transmitting the substantive data during a portion of the constituent time periods and transmitting "null" data during the remainder of the constituent time periods. Thus, over the predetermined time period, the substantive data is transmitted at an effective rate that is less than the predetermined fixed data transmission rate. The null data may be transmitted interspersed with the substantive data, and the determination of how to intersperse the null data with the substantive data may be according to an interpolation algorithm, such as Bresenham's algorithm.

Abstract translation: 第一站可连接到第二站，用于在预定时间段内向第二站发送预定的固定数量的数据，以实现预定的固定数据传输速率。 预定时间段由多个组成时间段组成。 通过在组成时间段的一部分期间发送实质数据，在预定时间段内从第一站向第二站发送小于预定固定数据量的实质数据量，并发送“零” 在组成时间段的剩余时间内的数据。 因此，在预定时间段内，实质数据以小于预定的固定数据传输速率的有效速率发送。 空数据可以被散布在实质数据中，并且如何用实体数据来填充空数据的确定可以根据诸如Bresenham算法的插值算法。

公开(公告)号：US5862343A

公开(公告)日：1999-01-19

申请号：US918943

申请日：1997-08-25

Applicant: Mark Landguth ,  Paul Cheng

Inventor： Mark Landguth ,  Paul Cheng

IPC: H04J3/16 ,  H04L1/00 ,  H04L12/64 ,  G06F3/00

CPC classification number: H04L12/6418 ,  H04J3/1647 ,  H04L2012/6427 ,  H04L2012/6454 ,  H04L2012/6459 ,  H04Q2213/13103 ,  H04Q2213/13106 ,  H04Q2213/13214 ,  H04Q2213/1322 ,  H04Q2213/13292 ,  H04Q2213/13299 ,  H04Q2213/1336 ,  H04Q2213/13389

Abstract: A network-to-CPU interface circuit interfaces an isochronous physical layer to an ISA bus such that a host CPU connected to the ISA bus can communicate with the isochronous physical layer. Inbound B-channel interface circuity is connectable to receive, from the isochronous physical layer, an inbound data stream which includes a plurality of B-channels time division multiplexed into time division multiplexed (TDM) frames. The TDM frames have a predetermined format that defines at least one logical stream such that each logical stream comprises those B-channels that are time division multiplexed into corresponding predetermined locations within the TDM frames. An inbound buffer portion of a memory is provided to hold the received inbound data stream, and an outbound buffer portion of the memory is provided for holding an outbound data stream which, like the inbound data stream, includes a plurality of B-channels time division multiplexed into time division multiplexed (TDM) frames. ISA bus interface circuitry is provided for channeling a selected inbound logical stream from the inbound memory buffer to the host CPU, via the ISA bus, in response to a request from the host CPU. The ISA bus interface circuitry is also for receiving a data stream from the host CPU, via the ISA bus, and for channeling that received data stream, as an outbound logical stream, to the TDM frames in the outbound memory buffer according to the predetermined format. Outbound B-channel interface circuity is provided to transmit the outbound data stream from the outbound memory buffer to the isochronous physical layer.

Abstract translation: 网络到CPU接口电路将同步物理层接口到ISA总线，使得连接到ISA总线的主机CPU能够与等时物理层进行通信。 入站B信道接口电路可连接从等时物理层接收包括多个时分复用到时分复用（TDM）帧的多个B信道的入站数据流。 TDM帧具有定义至少一个逻辑流的预定格式，使得每个逻辑流包括时分多路复用到TDM帧内相应的预定位置的那些B信道。 提供存储器的入站缓冲器部分以保持所接收的入站数据流，并且提供存储器的出站缓冲器部分用于保持出站数据流，其与入站数据流一样，包括多个B信道时分 多路复用到时分复用（TDM）帧。 提供ISA总线接口电路，用于响应于来自主机CPU的请求，将选定的入站逻辑流从入站存储器缓冲器经由ISA总线传送到主机CPU。 ISA总线接口电路还用于经由ISA总线从主机CPU接收数据流，并根据预定格式将接收到的数据流作为出站逻辑流传送到出站存储器缓冲器中的TDM帧 。 提供出站B通道接口电路，用于将出站数据流从出站存储器缓冲区发送到同步物理层。