公开(公告)号：US20110095381A1

公开(公告)日：2011-04-28

申请号：US11664853

申请日：2005-10-05

Applicant: Markus Müller ,  Benoît Froment

Inventor： Markus Müller ,  Benoît Froment

IPC: H01L29/49 ,  H01L21/336 ,  H01L21/28

CPC classification number: H01L21/28026 ,  H01L29/665

Abstract: A MOS transistor having its gate successively comprising an insulating layer, a metal silicide layer, a layer of a conductive encapsulation material, and a polysilicon layer.

Abstract translation: MOS晶体管，其栅极依次包括绝缘层，金属硅化物层，导电封装材料层和多晶硅层。

公开(公告)号：US07947583B2

公开(公告)日：2011-05-24

申请号：US11592398

申请日：2006-11-02

Applicant: Delphine Aime ,  Benoît Froment

Inventor： Delphine Aime ,  Benoît Froment

IPC: H01L21/425

CPC classification number: H01L29/66507 ,  H01L21/26513 ,  H01L21/28097

Abstract: An embodiment of a method for forming silicide areas of different thicknesses in a device comprising first and second silicon areas, comprising the steps of: implanting antimony or aluminum in the upper portion of the first silicon areas; covering the silicon areas with a metallic material; and heating the device to transform all or part of the silicon areas into silicide areas, whereby the silicide areas formed at the level of the first silicon areas are thinner than the silicide areas formed at the level of the second silicon areas.

Abstract translation: 一种用于在包括第一和第二硅区域的器件中形成不同厚度的硅化物区域的方法的实施例，包括以下步骤：在第一硅区域的上部注入锑或铝; 用金属材料覆盖硅区域; 并且加热该器件以将全部或部分硅区域转化为硅化物区域，由此形成在第一硅区域的层面处的硅化物区域比形成在第二硅片区域的硅化物区域薄。

公开(公告)号：US06366098B1

公开(公告)日：2002-04-02

申请号：US09336269

申请日：1999-06-18

Applicant: Benoît Froment

Inventor： Benoît Froment

IPC: G01N2722

CPC classification number: G01R27/2605 ,  G01R31/2884

Abstract: A test structure includes a single current-measuring means for measuring current between a supply terminal and ground, and first and second branches for measuring capacitance between first and second metal lines. The first branch includes a first switch coupled between the current-measuring means and the first line, and a second switch coupled between the first line and ground. Similarly, the second branch includes a third switch coupled between the current-measuring means and the second line, and a fourth switch coupled between the second line and ground. A method for testing a circuit is also provided. According to the method, the capacitance between first and second metal lines is calculated by: measuring a first current needed to bring the first line to the voltage of a first terminal while the other lines are at the voltage of a second terminal, measuring a second current needed to bring the second line to the voltage of the first terminal while the other lines are at the voltage of the second terminal, and measuring a third current needed to bring the first and second lines to the voltage of the first terminal while the other lines are at the voltage of the second terminal. The measurements are performed using a single current-measuring means.

Abstract translation: 测试结构包括用于测量电源端子和地之间的电流的单个电流测量装置，以及用于测量第一和第二金属线之间的电容的第一和第二支路。 第一分支包括耦合在电流测量装置和第一线之间的第一开关以及耦合在第一线与地之间的第二开关。 类似地，第二分支包括耦合在电流测量装置和第二线之间的第三开关，以及耦合在第二线与地之间的第四开关。 还提供了一种用于测试电路的方法。 根据该方法，通过以下步骤来计算第一和第二金属线之间的电容：测量使第一线路到第一端子的电压所需的第一电流，而其他线路处于第二端子的电压，测量第二线路的第二电流 将第二线路连接到第一端子的电压而其他线路处于第二端子的电压所需的电流，以及测量将第一和第二线路连接到第一端子的电压所需的第三电流，而另一条线路 线路处于第二端子的电压。 使用单个电流测量装置进行测量。

公开(公告)号：US07638427B2

公开(公告)日：2009-12-29

申请号：US11329358

申请日：2006-01-10

Applicant: Benoît Froment ,  Delphine Aime

Inventor： Benoît Froment ,  Delphine Aime

IPC: H01L21/4763 ,  H01L29/94

CPC classification number: H01L29/66507 ,  H01L21/28097 ,  H01L21/32105 ,  H01L29/4975 ,  H01L29/66545

Abstract: An MOS transistor with a fully silicided gate is produced by forming a silicide compound in the gate separately and independently of silicide portions located in source and drain zones of the transistor. To this end, the silicide portions of the source and drain zones are covered by substantially impermeable coatings. The coatings prevent the silicide portions of the source and drain zones from increasing in volume during separate and independent formation of the gate silicide compound. The silicide gate may thus be thicker than the silicide portions of the source and drain zones.

Abstract translation: 具有完全硅化栅的MOS晶体管通过在栅极中分开独立于位于晶体管的源极和漏极区中的硅化物部分独立地形成硅化物而产生。 为此，源极和漏极区域的硅化物部分被基本上不可渗透的涂层覆盖。 在单独和独立形成栅极硅化物化合物期间，涂层防止源极和漏极区的硅化物部分体积增加。 因此，硅化物栅极可以比源区和漏区的硅化物部分更厚。

公开(公告)号：US07018865B2

公开(公告)日：2006-03-28

申请号：US10873750

申请日：2004-06-21

Applicant: Benoît Froment ,  François Wacquant

Inventor： Benoît Froment ,  François Wacquant

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC classification number: H01L21/28518

Abstract: A semiconductor material is protected against the formation of a metal silicide by forming a layer of a silicon/germanium alloy on the material. The material which is protected belongs to a component of an integrated circuit comprising other components that have to be subjected to a siliciding operation. The method of protection includes depositing a layer of silicon/germanium alloy on the integrated circuit. The layer of silicon/germanium alloy is then removed from the areas to be silicided. A metal is then deposited on the structure and a metal silicide is formed therefrom. The unreacted metal and the metal/silicon/germanium ternary alloy that may have formed are removed, and the layer of silicon/germanium alloy is removed so as to expose the unsilicided component.

Abstract translation: 通过在材料上形成硅/锗合金层来保护半导体材料免受金属硅化物的形成。 被保护的材料属于集成电路的部件，该集成电路包括必须进行硅化操作的其它部件。 保护方法包括在集成电路上沉积一层硅/锗合金。 然后将硅/锗合金层从要被硅化的区域中取出。 然后在结构上沉积金属，由此形成金属硅化物。 去除可能形成的未反应的金属和金属/硅/锗三元合金，并除去硅/锗合金层，以暴露未被硅化的组分。

公开(公告)号：US06504380B2

公开(公告)日：2003-01-07

申请号：US09874896

申请日：2001-06-05

Applicant: Raul Andrés Bianchi ,  Benoît Froment

Inventor： Raul Andrés Bianchi ,  Benoît Froment

IPC: G01R3112

CPC classification number: H03M1/109 ,  H03M1/78

Abstract: A device includes a capacitive structure including an input node and n output nodes, r integrated capacitors connected in series between two adjacent nodes, an integrated capacitor connected between the input node and ground, an integrated capacitor connected between the nth output node and ground, and r capacitive branches connected in parallel between ground and each node of the capacitive structure including the first output node and the (n−1)th output node. Each branch may include r+1 series-connected integrated capacitors. Furthermore, the integrated capacitors of the capacitive structure are theoretically identical. The device may also include a charge source for charging each node of the capacitive structure. Additionally, a measurement circuit may measure the charge at each of the nodes of the structure, and a comparison circuit may compare each measured nodal charge value with a theoretical nodal charge value while taking into account a predetermined nodal tolerance.