公开(公告)号：US09985646B1

公开(公告)日：2018-05-29

申请号：US15787387

申请日：2017-10-18

Applicant: Schweitzer Engineering Laboratories, Inc.

Inventor： Travis C. Mallett

IPC: H03M3/00 ,  H03M1/10 ,  H03K3/017

CPC classification number: H03M3/378 ,  H03K3/017 ,  H03M1/1071 ,  H03M1/109 ,  H03M1/1095 ,  H03M1/38 ,  H03M3/458 ,  H03M3/494

Abstract: Disclosed are systems and methods for identifying and reporting failures of an analog-to-digital converter (ADC). Specifically, the systems and methods described herein evaluate quantization noise properties of ADCs, including delta-sigma ADCs and successive approximation register (SAR) ADCs, to verify functionality and/or identify failures. Quantization noise properties can be evaluated in the frequency domain by, for example, comparing RMS values, magnitudes, frequency spectrums, and the like, in various frequency bands to threshold values and/or to verify an expected noise shape. Quantization noise properties can additionally or alternatively be evaluated in the time domain by, for example, comparing counts of pulse widths, average pulse widths, and/or number of transitions within a sequence of pulses to threshold values and/or to similar identifiable characteristics in other pulse width bands.

公开(公告)号：US09692437B2

公开(公告)日：2017-06-27

申请号：US15083096

申请日：2016-03-28

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Young-deuk Jeon ,  Min-Hyung Cho ,  Yi-Gyeong Kim ,  Chun-Gi Lyuh

IPC: H03M1/10 ,  H03M1/12

CPC classification number: H03M1/109 ,  H03M1/12

Abstract: Provided is an analog-to-digital converting device. The analog-to-digital converting device may include a determination circuit that determination whether a reference digital signal or a determination digital signal obtained by conversion of a reference voltage or a determination voltage matches a test pattern for the reference voltage, and it is possible to monitor whether the analog-to-digital converting device normally operates, according to whether there is matching.

公开(公告)号：US20160336951A1

公开(公告)日：2016-11-17

申请号：US15083096

申请日：2016-03-28

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Young-deuk JEON ,  MIN-HYUNG CHO ,  Yi-Gyeong KIM ,  Chun-Gi LYUH

IPC: H03M1/10 ,  H03M1/34

CPC classification number: H03M1/109 ,  H03M1/12

Abstract: Provided is an analog-to-digital converting device. The analog-to-digital converting device may include a determination circuit that determination whether a reference digital signal or a determination digital signal obtained by conversion of a reference voltage or a determination voltage matches a test pattern for the reference voltage, and it is possible to monitor whether the analog-to-digital converting device normally operates, according to whether there is matching.

Abstract translation: 提供了一种模拟 - 数字转换装置。 模拟数字转换装置可以包括确定电路，其确定参考数字信号或通过转换参考电压或确定电压获得的确定数字信号是否与参考电压的测试模式匹配，并且可以 根据是否存在匹配，监控模数转换设备是否正常运行。

公开(公告)号：US09438262B1

公开(公告)日：2016-09-06

申请号：US14745653

申请日：2015-06-22

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Tao Chen ,  Douglas A. Garrity ,  Xiankun Jin

IPC: H03M1/10 ,  H03M1/12 ,  H03H19/00

CPC classification number: H03M1/109 ,  H03H19/004 ,  H03M1/12

Abstract: A method and circuit for testing an analog-to-digital converter (ADC) are provided. The method comprises: coupling a single-ended output of an analog signal source to a differential input of an amplifier; coupling a differential output of the amplifier to a differential input of the ADC; alternately providing first and second test signals from the single-ended output of the analog signal source to first and second input terminals of the differential input of the amplifier; amplifying the first and second test signals to generate amplified differential signals at the differential output of the amplifier; providing the amplified differential signals to the differential input of the ADC; and determining if an output of the ADC is as expected. An offset may also be provided to the differential output of the amplifier. The method allows an ADC having a differential input to be tested using a digital-to-analog converter (DAC) having a single-ended output.

Abstract translation: 提供了一种用于测试模数转换器（ADC）的方法和电路。 该方法包括：将模拟信号源的单端输出耦合到放大器的差分输入; 将放大器的差分输出耦合到ADC的差分输入; 交替地将模拟信号源的单端输出的第一和第二测试信号提供给放大器的差分输入的第一和第二输入端; 放大第一和第二测试信号以在放大器的差分输出处产生放大的差分信号; 将放大的差分信号提供给ADC的差分输入; 并确定ADC的输出是否如预期的那样。 还可以向放大器的差分输出提供偏移。 该方法允许具有差分输入的ADC使用具有单端输出的数模转换器（DAC）进行测试。

公开(公告)号：US09166608B1

公开(公告)日：2015-10-20

申请号：US14731471

申请日：2015-06-05

Applicant: IMEC VZW

Inventor： Kazuaki Deguchi ,  Bob Verbruggen ,  Jan Craninckx

IPC: H03M1/10 ,  H03M1/06 ,  H03M1/00 ,  H03M1/46 ,  H03M1/12

CPC classification number: H03M1/0604 ,  H03M1/00 ,  H03M1/002 ,  H03M1/1071 ,  H03M1/109 ,  H03M1/12 ,  H03M1/1215 ,  H03M1/14 ,  H03M1/468 ,  H03M2201/4233

Abstract: Methods and devices herein relate to a method for estimating bandwidth mismatch in a time-interleaved A/D converter. An example method includes precharging terminals of capacitors to a first state in each channel of a plurality of channels and sampling a reference analog input voltage signal (Vref) applied via a first switchable path whereby the sampled input voltage signal is received at first terminals of the capacitors. The method further includes setting the second terminals of each channel to a second state. The method also includes applying the reference analog input voltage signal to the first terminals via a second switchable path, and thereby creating on the first terminals a non-zero settling error. The method additionally includes quantizing the settling error to obtain an estimate of the non-zero settling error. The method yet further includes comparing the estimates of the non-zero settling errors and deriving an estimation of the bandwidth mismatch.

Abstract translation: 这里的方法和装置涉及用于估计时间交织的A / D转换器中的带宽不匹配的方法。 示例性方法包括：在多个通道的每个通道中将电容器的端子预充电到第一状态，并对通过第一可切换路径施加的参考模拟输入电压信号（Vref）进行采样，由此在第一端子处接收采样的输入电压信号 电容器 该方法还包括将每个信道的第二终端设置为第二状态。 该方法还包括经由第二可切换路径将参考模拟输入电压信号施加到第一端子，从而在第一端子上产生非零稳定误差。 该方法另外包括量化沉降误差以获得非零建立误差的估计。 该方法还包括比较非零建立误差的估计并导出带宽不匹配的估计。

公开(公告)号：US09088294B2

公开(公告)日：2015-07-21

申请号：US14272477

申请日：2014-05-07

Applicant: Infineon Technologies AG

Inventor： Heinz Mattes

IPC: H03M1/10 ,  H03M1/12

CPC classification number: H03M1/1071 ,  H03M1/109 ,  H03M1/12

Abstract: A method and apparatus for characterizing an A/D converter are provided. The A/D converter is configured to convert an input signal into a digital output signal. The method and apparatus may provide: applying an input signal to the A/D converter that in a first phase at least includes a gradient of a rising exponential function with Euler's number as the base, and in a further phase has a profile of a falling exponential function with Euler's number as the base, integrating a digital output signal associated with the A/D converter during the first phase to provide a first sum, integrating the digital output signal associated with the A/D converter during the further phase to provide a second sum, and calculating from the first sum and the second sum at least a gain error of the A/D converter and/or a zero point error of the A/D converter.

Abstract translation: 提供一种用于表征A / D转换器的方法和装置。 A / D转换器被配置为将输入信号转换为数字输出信号。 该方法和装置可以提供：向A / D转换器施加输入信号，其在第一阶段中至少包括以欧拉数为基的上升指数函数的梯度，并且在另一阶段中具有下降曲线 以欧拉数为基准的指数函数，在第一阶段积分与A / D转换器相关联的数字输出信号以提供第一和，在进一步阶段积分与A / D转换器相关联的数字输出信号，以提供 并且从第一和和第二和计算A / D转换器的至少一个增益误差和/或A / D转换器的零点误差。

公开(公告)号：US09077362B2

公开(公告)日：2015-07-07

申请号：US14445765

申请日：2014-07-29

Applicant: STMicroelectronics International N.V.

Inventor： Ravindranath Ramalingaiah Munnan ,  Raghu Ravindran ,  Ravi Shekhar

IPC: H03M1/10 ,  H03M1/14 ,  H03M1/66

CPC classification number: H03M1/109 ,  H03M1/144 ,  H03M1/66

Abstract: A chip with a built-in self-test (BIST) component capable of testing the linearity of an ADC is described herein. The BIST component uses hardware registers to facilitate a sliding histogram technique to save space on the chip. A subset of detected digital codes are analyzed, and DNL and INL calculations are performed by a controller to determine whether any of the digital codes in the subset exceed maximum or minimum DNL and INL thresholds. New digital codes being detected by the ADC are added to the subset as lower-value digital codes are pushed out of the subset, maintaining the same number of digital codes being analyzed as the subset moves from lower codes detected during lower voltages to higher codes detected at higher voltages. A synchronizer and pointer ensure that the subset moves through the digital codes at the same rate as the analog input ramp source.

Abstract translation: 本文描述了具有能够测试ADC的线性度的内置自测（BIST）组件的芯片。 BIST组件使用硬件寄存器来促进滑动直方图技术，以节省芯片上的空间。 分析检测到的数字代码的子集，并由控制器执行DNL和INL计算，以确定子集中的任何数字代码是否超过最大或最小DNL和INL阈值。 当ADC将低值数字代码从子集中推出时，由ADC检测到的新数字代码被添加到子集中，当子集从较低电压下检测到的较低代码移动到检测到的较高代码时，保持相同数量的数字代码被分析 在较高的电压。 同步器和指针确保子集以与模拟输入斜坡源相同的速率移动数字代码。

公开(公告)号：US20150188557A1

公开(公告)日：2015-07-02

申请号：US14577618

申请日：2014-12-19

Applicant: Renesas Electronics Corporation

Inventor： Takahiro UMEZAKI ,  Yasutaka Horikoshi ,  Takehiro Mikami

IPC: H03M1/10 ,  H03M1/38

CPC classification number: H03M1/109 ,  H03M1/38

Abstract: To determine the accuracy of an AD converter more simply than in the related art, a semiconductor device includes a successive approximation AD converter. The AD converter includes one or a plurality of testing capacitors used in a test mode, separately from a C-DAC used for AD conversion in a normal mode. In the test mode, the accuracy of a capacitor under test among a plurality of capacitors configuring the C-DAC is determined by comparing a potential occurring in the capacitor under test and a potential occurring in the testing capacitors.

Abstract translation: 为了比现有技术更简单地确定AD转换器的精度，半导体器件包括逐次逼近AD转换器。 AD转换器包括与在正常模式下用于AD转换的C-DAC分开的在测试模式中使用的一个或多个测试电容器。 在测试模式下，通过比较被测电容器中发生的电位和测试电容器中出现的电位，来确定构成C-DAC的多个电容器中的被测电容器的精度。

公开(公告)号：US08803716B1

公开(公告)日：2014-08-12

申请号：US13859954

申请日：2013-04-10

Applicant: STMicroelectronics International N.V.

Inventor： Ravindranath Ramalingaiah Munnan ,  Raghu Ravindran ,  Ravi Shekhar

IPC: H03M1/10

CPC classification number: H03M1/109 ,  H03M1/144 ,  H03M1/66

Abstract: A chip with a built-in self-test (BIST) component capable of testing the linearity of an ADC is described herein. The BIST component uses hardware registers to facilitate a sliding histogram technique to save space on the chip. A subset of detected digital codes are analyzed, and DNL and INL calculations are performed by a controller to determine whether any of the digital codes in the subset exceed maximum or minimum DNL and INL thresholds. New digital codes being detected by the ADC are added to the subset as lower-value digital codes are pushed out of the subset, maintaining the same number of digital codes being analyzed as the subset moves from lower codes detected during lower voltages to higher codes detected at higher voltages. A synchronizer and pointer ensure that the subset moves through the digital codes at the same rate as the analog input ramp source.

Abstract translation: 本文描述了具有能够测试ADC的线性度的内置自测（BIST）组件的芯片。 BIST组件使用硬件寄存器来促进滑动直方图技术，以节省芯片上的空间。 分析检测到的数字代码的子集，并由控制器执行DNL和INL计算，以确定子集中的任何数字代码是否超过最大或最小DNL和INL阈值。 当ADC将低值数字代码从子集中推出时，由ADC检测到的新数字代码被添加到子集中，当子集从较低电压下检测到的较低代码移动到检测到的较高代码时，保持相同数量的数字代码被分析 在较高的电压。 同步器和指针确保子集以与模拟输入斜坡源相同的速率移动数字代码。

公开(公告)号：US08706445B2

公开(公告)日：2014-04-22

申请号：US12507320

申请日：2009-07-22

Applicant: Koji Asami

Inventor： Koji Asami

IPC: G06F17/18 ,  H03M1/12

CPC classification number: H03M1/109 ,  H03M1/12

Abstract: Provided is a measurement apparatus that measures a characteristic of an AD converter, comprising a signal supplying section that supplies the AD converter with an analog input signal having a prescribed waveform; an acquiring section that acquires a digital output signal output by the AD converter as a result of sampling the analog input signal; a measured histogram generating section that generates a histogram of the digital output signal; and a range calculating section that calculates at least one of an analog value corresponding to a lower limit and an analog value corresponding to an upper limit of a prescribed digital range, based on at least one of (i) a frequency corresponding to digital values, in a measured histogram obtained by measuring the digital output signal, that are less than or equal to the digital range and (ii) a frequency corresponding to digital values in the measured histogram that are greater than or equal to the digital range.

Abstract translation: 提供了一种测量AD转换器的特性的测量装置，包括：向AD转换器提供具有规定波形的模拟输入信号的信号提供部; 获取部，其获取由所述AD转换器输出的数字输出信号作为对所述模拟输入信号进行采样的结果; 测量的直方图生成部分，其生成数字输出信号的直方图; 以及范围计算部，其基于以下中的至少一个来计算与下限相对应的模拟值和对应于规定数字范围的上限的模拟值中的至少一个：（i）对应于数字值的频率， 在通过测量小于或等于数字范围的数字输出信号获得的测量直方图中，以及（ii）对应于大于或等于数字范围的测量直方图中的数字值的频率。