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1.发明授权Method, system and computer program product for determining required precision in fixed-point divide operations 有权用于确定定点分割操作所需精度的方法，系统和计算机程序产品公开(公告)号：US08402078B2
公开(公告)日：2013-03-19
申请号：US12037207
申请日：2008-02-26
IPC分类号： G06F7/52
CPC分类号： G06F7/535 , G06F2207/5355
摘要： A method, computer program product and a system for controlling a fixed point division operation are provided. The method includes: receiving an instruction to perform a division operation for a dividend and a divisor, the operation comprising a maximum number of iterations to produce a quotient having a maximum precision; calculating a magnitude of at least one of the dividend and the divisor; determining a quotient precision based on the magnitude; and computing a required number of iterations needed to produce the quotient precision and performing the number of iterations.
摘要翻译： 提供了一种用于控制固定点分割操作的方法，计算机程序产品和系统。 该方法包括：接收执行对除数和除数的除法运算的指令，所述操作包括最大迭代次数以产生具有最大精度的商; 计算至少一个股息和除数的幅度; 基于幅度确定商精度; 并计算产生商精度和执行迭代次数所需的迭代次数。
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公开(公告)号：US5539332A
公开(公告)日：1996-07-23
申请号：US331436
申请日：1994-10-31
申请人： Martin S. Schmookler
发明人： Martin S. Schmookler
摘要： An evaluation tree circuit is disclosed that produces a generate, a propagate, and a zero output for use in carry lookahead adders. Another evaluation tree circuit is disclosed that merges the generate, propagate, and zero signals from several adjacent bits or groups of bits. These evaluation trees may be used in self-resetting CMOS or CVSL circuits. They can be used to reduce the number of levels of logic in a carry lookahead adder. They can also be used to form a magnitude comparator, which is also disclosed.
摘要翻译： 公开了一种评估树电路，其产生用于携带前瞻加法器的生成，传播和零输出。 公开了另一个评估树电路，其合并来自几个相邻位或位组的生成，传播和零信号。 这些评估树可以用于自复位CMOS或CVSL电路。 它们可以用于减少进位前瞻加法器中逻辑电平的数量。 它们也可以用于形成幅度比较器，其也被公开。
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3.发明申请METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR DETERMINING REQUIRED PRECISION IN FIXED-POINT DIVIDE OPERATIONS 有权方法，系统和计算机程序产品用于确定固定点操作中所需的精度公开(公告)号：US20090216824A1
公开(公告)日：2009-08-27
申请号：US12037207
申请日：2008-02-26
IPC分类号： G06F7/487
CPC分类号： G06F7/535 , G06F2207/5355
摘要： A method, computer program product and a system for controlling a fixed point division operation are provided. The method includes: receiving an instruction to perform a division operation for a dividend and a divisor, the operation comprising a maximum number of iterations to produce a quotient having a maximum precision; calculating a magnitude of at least one of the dividend and the divisor; determining a quotient precision based on the magnitude; and computing a required number of iterations needed to produce the quotient precision and performing the number of iterations.
摘要翻译： 提供了一种用于控制固定点分割操作的方法，计算机程序产品和系统。 该方法包括：接收执行对除数和除数的除法运算的指令，所述操作包括最大迭代次数以产生具有最大精度的商; 计算至少一个股息和除数的幅度; 基于幅度确定商精度; 并计算产生商精度和执行迭代次数所需的迭代次数。
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4.发明授权Method and system for verifying a digital circuit design including dynamic circuit cells that utilize diverse circuit techniques 失效用于验证数字电路设计的方法和系统，包括利用多种电路技术的动态电路单元
公开(公告)号：US5930148A
公开(公告)日：1999-07-27
申请号：US767407
申请日：1996-12-16
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5031
摘要： A method and system are described, which utilize timing analysis to verify a digital circuit design that includes a plurality of dynamic logic circuit cells employing diverse circuit techniques and that may also include static logic circuit cells. For each dynamic circuit cell, a set of timing constraints is defined based upon the circuit technique employed by the associated dynamic logic circuit cell. Each timing constraint prevents a possible mode of failure of the associated dynamic logic circuit cell. The digital circuit design is then verified. The verification includes a determination of whether or not each dynamic logic circuit cell satisfies its respective set of timing constraints while connected to the other circuit cells. In an embodiment in which the digital circuit design includes a static logic circuit cell, the verification includes a verification that the static logic circuit cell has a correct inversion relationship between its input and output.
摘要翻译： 描述了一种方法和系统，其利用定时分析来验证包括采用多种电路技术的多个动态逻辑电路单元并且还可以包括静态逻辑电路单元的数字电路设计。 对于每个动态电路单元，基于由相关联的动态逻辑电路单元采用的电路技术来定义一组时序约束。 每个时序约束阻止相关联的动态逻辑电路单元的可能的故障模式。 然后验证数字电路设计。 验证包括确定每个动态逻辑电路单元在连接到其它电路单元时是否满足其各自的定时约束集合。 在数字电路设计包括静态逻辑电路单元的实施例中，验证包括静态逻辑电路单元在其输入和输出之间具有正确的反相关系的验证。
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公开(公告)号：US4771284A
公开(公告)日：1988-09-13
申请号：US896050
申请日：1986-08-13
IPC分类号： H03K19/017 , H03K19/177 , H04Q1/00
CPC分类号： H03K19/01721 , H03K19/17708
摘要： A programmable logic array having a plurality of electrically isolated input lines connected to an input circuit for providing an input signal to one of the plurality of input lines. Also included are a plurality of electrically isolated output lines positioned relative to the input lines to form an array having a plurality of non-conductive intersections. A plurality of programmable circuits, each positioned at a selected one of the intersections and interconnecting an adjacent input line, an adjacent output line and one of two output potentials that define one of two output states are provided. The programmable circuit is further connected to the input line such that when an input signal is received on the input line, the selected output potential representing one of the two output states is provided on the output line.
摘要翻译： 一种可编程逻辑阵列，其具有连接到输入电路的多个电隔离输入线，用于向多条输入线之一提供输入信号。 还包括多个电隔离输出线，其相对于输入线定位，以形成具有多个非导电交叉点的阵列。 提供多个可编程电路，每个可编程电路定位在所选交叉点中的一个并且互连相邻的输入线，相邻的输出线和限定两个输出状态之一的两个输出电位之一。 可编程电路还连接到输入线，使得当在输入线上接收到输入信号时，在输出线上提供表示两个输出状态之一的所选输出电位。
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6.发明授权Method, system and computer program product for detecting errors in fixed point division operation results 有权用于检测定点分割运算结果误差的方法，系统和计算机程序产品公开(公告)号：US08626816B2
公开(公告)日：2014-01-07
申请号：US12037408
申请日：2008-02-26
IPC分类号： G06F7/52
CPC分类号： G06F7/5375
摘要： A method, computer program product and a system for detecting errors in a result of a fixed-point division operation are provided. The method includes: receiving a result of a fixed-point division operation for a dividend and a divisor; performing a first comparison of the divisor and a remainder of the result; performing a second comparison of a sign of the dividend and a sign of the remainder; and determining whether the result is correct based on the first comparison and the second comparison.
摘要翻译： 提供了一种用于检测定点分割操作的结果中的错误的方法，计算机程序产品和系统。 该方法包括：接收除数和除数的定点除法运算结果; 执行除数和结果的其余部分的第一次比较; 对股息的符号和余数进行第二次比较; 以及基于所述第一比较和所述第二比较来确定所述结果是否正确。
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7.发明申请METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR VERIFYING FLOATING POINT DIVIDE OPERATION RESULTS 有权方法，系统和计算机程序产品用于验证浮点运算结果公开(公告)号：US20090216823A1
公开(公告)日：2009-08-27
申请号：US12036397
申请日：2008-02-25
CPC分类号： G06F7/4873
摘要： A method, system and computer program product for verifying a result of a floating point division operation are provided. The method includes: receiving a result of a floating point division operation for a dividend and a divisor; performing a comparison of a magnitude of a least significant bit (LSB) of the dividend and a magnitude of a most significant bit (MSB) of a remainder; and determining whether the result is correct based on the comparison.
摘要翻译： 提供了用于验证浮点除法运算结果的方法，系统和计算机程序产品。 该方法包括：接收分红和除数的浮点除法运算结果; 执行除数的最低有效位（LSB）的大小与余数的最高有效位（MSB）的大小的比较; 以及基于所述比较来确定所述结果是否正确。
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8.发明申请METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR VERIFYING FLOATING POINT SQUARE ROOT OPERATION RESULTS 有权方法，系统和计算机程序产品，用于验证浮点点平方根操作结果公开(公告)号：US20090216822A1
公开(公告)日：2009-08-27
申请号：US12036387
申请日：2008-02-25
CPC分类号： G06F7/483 , G06F7/5525
摘要： A method, system and computer program product for verifying a result of a floating point square root operation is provided. The method includes: receiving a result of a floating point square root operation for an operand; performing a comparison of a magnitude of a least significant bit (LSB) of the operand and a magnitude of a most significant bit (MSB) of a remainder; and determining whether the result is correct based on the comparison.
摘要翻译： 提供了用于验证浮点平方根操作的结果的方法，系统和计算机程序产品。 该方法包括：接收操作数的浮点平方根操作的结果; 执行操作数的最低有效位（LSB）的大小与余数的最高有效位（MSB）的大小的比较; 以及基于所述比较来确定所述结果是否正确。
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公开(公告)号：US5764549A
公开(公告)日：1998-06-09
申请号：US639573
申请日：1996-04-29
IPC分类号： G06F5/01
CPC分类号： G06F5/012
摘要： A device for aligning the radix point of an unaligned binary result of a floating point operation to a normalized or denormalized position is provided. The device comprises an alignment circuit that produces a shift alignment vector indicating the position of the most significant bit of the unaligned result that is set, when a normalized result is required, and that produces a shift alignment vector indicating the position of a bit of the unaligned result having the weight of a minimum allowable exponent for a given format, when a denormalized result is required. A shift register responsive to the alignment circuit shifts the unaligned result by the number of bits indicated by the shift alignment vector. The bit of the unaligned result having the weight of the minimum allowable exponent for the given format is determined by subtracting the binary value of the minimum allowable exponent from the binary value of the most significant bit of the unaligned result, wherein the difference indicates the number of bits from the most significant bit that the bit having the weight of the minimum allowable exponent is positioned.
摘要翻译： 提供了用于将浮点运算的未对齐二进制结果的基数与归一化或非归一化位置对准的装置。 该装置包括对准电路，当需要归一化结果时，该对准电路产生指示所设置的未对准结果的最高有效位的位置的移位对准矢量，并且产生一个移位对齐矢量，其指示位 当需要非规范化结果时，对于给定格式，具有最小可允许指数权重的未对齐结果。 响应于对准电路的移位寄存器将未对齐结果移位由移位对准矢量指示的位数。 通过从未对齐结果的最高有效位的二进制值中减去最小可允许指数的二进制值来确定具有给定格式的最小允许指数权重的未对齐结果的位，其中该差表示数字 来自最高有效位的位具有最小允许指数的权重的位被定位。
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公开(公告)号：US5636156A
公开(公告)日：1997-06-03
申请号：US730166
申请日：1996-10-15
CPC分类号： G06F7/508 , G06F2207/3836 , G06F2207/5063
摘要： An adder circuit is disclosed having an improved carry lookahead arrangement. The number of carry lookahead stages required is log n, where n is equal to the number of bits in the adder. This arrangement has fanout limit based on the number of sets of propagate and generate signals which can be combined at each bit location of each stage. For example, if two-way merge circuits are used to combine two sets of signals together, then the maximum fanout from the previous stage would be limited to two (2). If four-way merge circuits were used, then the fanout would be limited to four (4). This low fanout is achieved without increasing the number of stages by overlapping the groups that are combined in each step.
摘要翻译： 公开了一种具有改进的进位前视装置的加法器电路。 所需的进位前视级数是log n，其中n等于加法器中的位数。 这种布置具有基于传播集合的数量的扇出限制，并且可以在每个阶段的每个比特位置处产生可以组合的信号。 例如，如果使用双向合并电路将两组信号组合在一起，则来自前一级的最大扇出输出将被限制为两（2）。 如果使用四路合并电路，则扇出将限制为四（4）。 通过重叠在每个步骤中组合的组来实现这种低扇出，而不增加级数。
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