公开(公告)号：US20170180156A1

公开(公告)日：2017-06-22

申请号：US15453262

申请日：2017-03-08

申请人： Marvell World Trade Ltd.

发明人： Eitan Joshua ,  Shaul Chapman ,  Erez Amit ,  Noam Mizrahi ,  Moshe Raz ,  Husam Khshaiboun ,  Amit Shmilovich ,  Sujat Jamil ,  Frank O'Bleness

IPC分类号： H04L12/46 ,  G06F12/0811 ,  G06F12/0815

CPC分类号： H04L12/4637 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/0815 ,  G06F13/1657 ,  G06F15/17375 ,  G06F2212/283 ,  G06F2212/621 ,  H04L2012/421

摘要： In various embodiments, the present disclosure provides a system comprising a first plurality of processing cores, ones of the first plurality of processing cores coupled to a respective core interface module among a first plurality of core interface modules, the first plurality of core interface modules configured to be coupled to form in a first ring network of processing cores; a second plurality of processing cores, ones of the second plurality of processing cores coupled to a respective core interface module among a second plurality of core interface modules, the second plurality of core interface modules configured to be coupled to form a second ring network of processing cores; a first global interface module to form an interface between the first ring network and a third ring network; and a second global interface module to form an interface between the second ring network and the third ring network.

公开(公告)号：US20140201444A1

公开(公告)日：2014-07-17

申请号：US14161362

申请日：2014-01-22

申请人： Marvell World Trade Ltd.

发明人： Eitan Joshua ,  Shaul Chapman ,  Erez Amit ,  Moshe Raz ,  Amit Shmilovich

IPC分类号： G06F12/08

CPC分类号： H04L12/4637 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/0815 ,  G06F13/1657 ,  G06F15/17375 ,  G06F2212/283 ,  G06F2212/621 ,  H04L2012/421

摘要： In various embodiments, the present disclosure provides a system comprising a first plurality of processing cores, ones of the first plurality of processing cores coupled to a respective core interface module among a first plurality of core interface modules, the first plurality of core interface modules configured to be coupled to form in a first ring network of processing cores; a second plurality of processing cores, ones of the second plurality of processing cores coupled to a respective core interface module among a second plurality of core interface modules, the second plurality of core interface modules configured to be coupled to form a second ring network of processing cores; a first global interface module to form an interface between the first ring network and a third ring network; and a second global interface module to form an interface between the second ring network and the third ring network.

公开(公告)号：US09521011B2

公开(公告)日：2016-12-13

申请号：US14161362

申请日：2014-01-22

申请人： Marvell World Trade Ltd.

发明人： Eitan Joshua ,  Shaul Chapman ,  Erez Amit ,  Moshe Raz ,  Amit Shmilovich

IPC分类号： H04L12/46 ,  G06F12/08 ,  G06F13/16 ,  G06F15/173 ,  H04L12/42

CPC分类号： H04L12/4637 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/0815 ,  G06F13/1657 ,  G06F15/17375 ,  G06F2212/283 ,  G06F2212/621 ,  H04L2012/421

摘要： In various embodiments, the present disclosure provides a system comprising a first plurality of processing cores, ones of the first plurality of processing cores coupled to a respective core interface module among a first plurality of core interface modules, the first plurality of core interface modules configured to be coupled to form in a first ring network of processing cores; a second plurality of processing cores, ones of the second plurality of processing cores coupled to a respective core interface module among a second plurality of core interface modules, the second plurality of core interface modules configured to be coupled to form a second ring network of processing cores; a first global interface module to form an interface between the first ring network and a third ring network; and a second global interface module to form an interface between the second ring network and the third ring network.

公开(公告)号：US10230542B2

公开(公告)日：2019-03-12

申请号：US15453262

申请日：2017-03-08

申请人： Marvell World Trade Ltd.

发明人： Eitan Joshua ,  Shaul Chapman ,  Erez Amit ,  Noam Mizrahi ,  Moshe Raz ,  Husam Khshaiboun ,  Amit Shmilovich ,  Sujat Jamil ,  Frank O'Bleness

IPC分类号： H04L12/46 ,  G06F12/0813 ,  G06F12/0815 ,  G06F13/16 ,  G06F15/173 ,  G06F12/0811 ,  H04L12/42

摘要： In various embodiments, the present disclosure provides a system comprising a first plurality of processing cores, ones of the first plurality of processing cores coupled to a respective core interface module among a first plurality of core interface modules, the first plurality of core interface modules configured to be coupled to form in a first ring network of processing cores; a second plurality of processing cores, ones of the second plurality of processing cores coupled to a respective core interface module among a second plurality of core interface modules, the second plurality of core interface modules configured to be coupled to form a second ring network of processing cores; a first global interface module to form an interface between the first ring network and a third ring network; and a second global interface module to form an interface between the second ring network and the third ring network.

公开(公告)号：US20140201472A1

公开(公告)日：2014-07-17

申请号：US14161423

申请日：2014-01-22

申请人： Marvell World Trade Ltd.

发明人： Eitan Joshua ,  Amit Shmilovich ,  Moshe Raz ,  Shaul Chapman ,  Erez Amit

IPC分类号： G06F13/16

CPC分类号： H04L12/4637 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/0815 ,  G06F13/1657 ,  G06F15/17375 ,  G06F2212/283 ,  G06F2212/621 ,  H04L2012/421

摘要： In various embodiments, the present disclosure provides a system comprising a first plurality of processing cores, ones of the first plurality of processing cores coupled to a respective core interface module among a first plurality of core interface modules, the first plurality of core interface modules configured to be coupled to form in a first ring network of processing cores; a second plurality of processing cores, ones of the second plurality of processing cores coupled to a respective core interface module among a second plurality of core interface modules, the second plurality of core interface modules configured to be coupled to form a second ring network of processing cores; a first global interface module to form an interface between the first ring network and a third ring network; and a second global interface module to form an interface between the second ring network and the third ring network.

公开(公告)号：US20140201326A1

公开(公告)日：2014-07-17

申请号：US14155773

申请日：2014-01-15

申请人： Marvell World Trade Ltd.

发明人： Eitan Joshua ,  Shaul Chapman ,  Erez Amit ,  Noam Mizrahi ,  Moshe Raz ,  Husam Khshaiboun ,  Amit Shmilovich ,  Sujat Jamil ,  Frank O'Bleness

IPC分类号： H04L12/46

CPC分类号： H04L12/4637 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/0815 ,  G06F13/1657 ,  G06F15/17375 ,  G06F2212/283 ,  G06F2212/621 ,  H04L2012/421

摘要： In various embodiments, the present disclosure provides a system comprising a first plurality of processing cores, ones of the first plurality of processing cores coupled to a respective core interface module among a first plurality of core interface modules, the first plurality of core interface modules configured to be coupled to form in a first ring network of processing cores; a second plurality of processing cores, ones of the second plurality of processing cores coupled to a respective core interface module among a second plurality of core interface modules, the second plurality of core interface modules configured to be coupled to form a second ring network of processing cores; a first global interface module to form an interface between the first ring network and a third ring network; and a second global interface module to form an interface between the second ring network and the third ring network.