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1.发明授权Method for automating top-down design processing for the design of LSI functions and LSI mask layouts 失效自动设计LSI功能和LSI面板布局的自顶向下设计处理方法
公开(公告)号：US5963730A
公开(公告)日：1999-10-05
申请号：US717670
申请日：1996-09-23
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5072
摘要： A netlist between functional macros is entered. Based on the netlist, an outline layout process for a functional macro is performed and physical specifications for the functional macro are determined from an outline layout produced by the outline layout process. Thereafter, a logic synthesis process is performed on the basis of the physical specifications determined. Based on the outline layout, a logic, obtained by the logic synthesis, is laid out. This makes it possible to reduce the number of times a circuit synthesis process is redone, taking into account a laying-out at an upper-stage functional design process in which no gate level is specified. For this reason, an improved LSI automatic design method is provided which is able to complete an LSI layout design, in which the LSI area and the LSI delay value are optimized, in a short period of time.
摘要翻译： 输入功能宏之间的网表。 基于网表，执行用于功能宏的轮廓布局处理，并且根据由轮廓布局处理产生的轮廓布局来确定功能宏的物理规格。 此后，基于所确定的物理规格执行逻辑合成处理。 基于大纲布局，通过逻辑综合得到逻辑。 这使得可以减少电路合成过程被重做的次数，同时考虑到在没有指定门级的上级功能设计过程中的布局。 因此，提供了一种改进的LSI自动设计方法，其能够在短时间内完成LSI面积和LSI延迟值被优化的LSI布局设计。
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公开(公告)号：US5673200A
公开(公告)日：1997-09-30
申请号：US667284
申请日：1996-06-20
CPC分类号： G06F17/505
摘要： In synthesizing a gate level logic circuit using a computer based on behavioral description of LSI, a logic circuit is first synthesized based on the behavioral description and, then, its power consumption is obtained from the total number of operations. Thereafter, a specific signal propagation path having a larger power consumption is found out from a plurality of signal propagation paths in the logic circuit. A partial logic circuit consisting of logic elements positioned on the specific signal propagation path is optimized in the number of level, thereby creating an optimized partial circuit. Thereafter, obtained is a power consumption of a logic circuit consisting of the optimized partial circuit and the remaining circuit other than the circuit portion optimized. When thus obtained power consumption is small, the partial circuit being not optimized is replaced by the above optimized partial circuit. Accordingly, it becomes possible to reduce overall power consumption while adequately maintaining an area and speed performance of the logic circuit.
摘要翻译： 在使用基于LSI的行为描述的计算机合成门级逻辑电路时，首先基于行为描述合成逻辑电路，然后从总操作数获得其功耗。 此后，从逻辑电路中的多个信号传播路径中找出具有较大功耗的特定信号传播路径。 由位于特定信号传播路径上的逻辑元件组成的部分逻辑电路在电平数量上被优化，从而产生优化的部分电路。 此后，获得的是由优化的部分电路和除优化的电路部分之外的剩余电路组成的逻辑电路的功耗。 当这样获得的功耗小时，未优化的部分电路被上述优化的部分电路所取代。 因此，可以在充分维持逻辑电路的面积和速度性能的同时降低总体功耗。
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3.发明授权Clock distribution circuit with clock branch circuits connected to outgoing and return lines and outputting synchronized clock signals by summing time integrals of clock signals on the outgoing and return lines 失效时钟分配电路，其时钟分支电路连接到输出和返回线，并通过对输出和返回线上的时钟信号的时间积分求和来输出同步时钟信号
公开(公告)号：US5896055A
公开(公告)日：1999-04-20
申请号：US755817
申请日：1996-11-26
CPC分类号： G06F1/10
摘要： A layout area includes a clock interconnection consisting of an upward interconnection and a downward interconnection. The upward interconnection extends from the output terminal of a clock buffer which receives an external clock signal to a turning point while passing along the vicinity of a plurality of flip-flops. The downward interconnection extends from the turning point to a free end, reversing along the upward interconnection. Clock branch circuits are provided in the vicinity of the flip-flops. The clock branch circuits have a function of letting a third clock signal make a transition when the sum of the time integral of a first clock signal on the upward interconnection and the time integral of a second clock signal on the downward interconnection has become equal to the time integral for one pulse of one of the first clock signal and the second clock signal.
摘要翻译： 布局区域包括由向上互连和向下互连组成的时钟互连。 向上互连从时钟缓冲器的输出端子延伸，该时钟缓冲器在沿着多个触发器的附近通过时接收外部时钟信号到转折点。 向下的互连从转折点延伸到自由端，沿着向上的互连方向反转。 在触发器附近提供时钟分支电路。 时钟分支电路具有使第三时钟信号在向上互连上的第一时钟信号的时间积分与下行互连上的第二时钟信号的时间积分的和与 第一时钟信号和第二时钟信号之一的一个脉冲的时间积分。
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4.发明授权Method and apparatus for automatically arranging circuit elements in data-path circuit 失效用于在数据路径电路中自动布置电路元件的方法和装置
公开(公告)号：US5657243A
公开(公告)日：1997-08-12
申请号：US510673
申请日：1995-08-03
CPC分类号： G06F17/5068
摘要： An automatic layout of a data-path circuit, whose performance and area are optimized, requires to input a data-path circuit, produce an external terminal directive branch having a start point placed on an input terminal group of the data-path circuit and an end point placed on an output terminal group of the same, and produce in-circuit directive branches corresponding to respective connecting lines between two circuit elements in the data-path circuit, each in-circuit directive branch having a start point placed on one circuit element supplying a signal to a related connecting line and an end point placed on the other circuit element receiving the signal from the same connecting line. Subsequently, a group circuit is produced based on the relationship between the in-circuit directive branches and the circuit elements, the group circuit comprising a plurality of circuit elements performing a series of logic processing per 1-bit signal. A layout evaluation is then produced so as to comprise an evaluation satisfying a requirement that a direction of the external terminal directive branch is met with directions of the in-circuit directive branches. Thereafter, the layout of circuit elements is optimized based on the layout evaluation and the resultant layout is outputted.
摘要翻译： 数据路径电路的自动布局，其性能和面积被优化，需要输入数据路径电路，产生具有放置在数据路径电路的输入端子组上的起始点的外部终端指令分支，以及 终端放置在其输出端子组上，并且产生与数据通路电路中的两个电路元件之间的相应连接线相对应的在线指向分支，每个在线指向分支具有放置在一个电路元件上的起始点 向相关的连接线提供信号，并将另一个电路元件上的终点提供在从相同的连接线接收信号的位置上。 随后，基于在线指令分支和电路元件之间的关系产生组电路，组电路包括对每1位信号执行一系列逻辑处理的多个电路元件。 然后产生布局评估，以便包括满足外部终端指令分支的方向满足在线指令分支的指示的要求的评估。 此后，基于布局评估优化电路元件的布局，并输出结果布局。
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公开(公告)号：US5490083A
公开(公告)日：1996-02-06
申请号：US130385
申请日：1993-10-01
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5045
摘要： The logic elements and net list contained in a logic circuit are inputted to an electronic calculator. The total number N1 of primary adjacent logic circuits which are connected directly to all the logic elements contained in the foregoing logic circuit, respectively is calculated from the inputted logic elements and net list. The total number N2 of primary and secondary adjacent logic circuits, which is the sum of the foregoing total number N1 of primary adjacent logic circuits and the total number of secondary adjacent logic circuits which are connected directly to the primary adjacent logic circuits, respectively, is calculated from the inputted logic elements and net list. The difference between the logarithmic value of the foregoing total number N1 of primary adjacent logic circuits and the logarithmic value of the foregoing total number N2 of primary and secondary adjacent logic circuits is calculated as a value for classification which characterizes the aforesaid logic circuit.
摘要翻译： 包含在逻辑电路中的逻辑元件和网络列表被输入到电子计算器。 从输入的逻辑元件和网络列表中分别计算直接连接到上述逻辑电路中包含的所有逻辑元件的主相邻逻辑电路的总数N1。 主相邻逻辑电路的总数N2是主相邻逻辑电路的前述总数N1和直接连接到主相邻逻辑电路的次相邻逻辑电路的总数之和，分别为 从输入的逻辑元素和网络列表中计算。 主相邻逻辑电路的前述总数N1的对数值与初级和次级相邻逻辑电路的前述总数N2的对数值之间的差被计算为表征上述逻辑电路的分类值。
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公开(公告)号：US06499133B1
公开(公告)日：2002-12-24
申请号：US09527474
申请日：2000-03-17
IPC分类号： G06F945
CPC分类号： G06F17/5072
摘要： An initial arrangement is effected based on a net list and a cell library. Combination functions are extracted from a cost function. An optimum estimated temperature is calculated based on the difference between values of the cost function before and after two adjacent elements that have been selected randomly from elements to be arranged are interchanged in position, while near-optimum estimated temperatures are calculated based on the differences between respective values of the combination functions before and after the positional interchange. Of the near-optimum estimated temperatures, those lower than the optimum estimated temperature are recorded in a temperature schedule list together with the optimum estimated temperature. Thereafter, the Monte-Carlo method based on a random positional interchange between the elements to be arranged using the cost function is executed in order of the decreasing temperatures recorded in the temperature schedule list, whereby the initial arrangement is improved.
摘要翻译： 基于网络列表和小区库来实现初始安排。 从成本函数中提取组合函数。 基于成本函数的值之间的差值来计算最佳估计温度，所述两个相邻元素之间的差异是从要排列的元素随机选择的两个相邻元素之间的位置互换的，而近似最佳估计温度是基于 组合功能的相应值在位置交换之前和之后。 在近似最佳估计温度下，低于最佳估计温度的温度与最佳估计温度一起记录在温度调度表中。 此后，基于使用成本函数排列的要素之间的随机位置交换的蒙特卡罗方法按照记录在温度调度列表中的降低温度的顺序执行，从而提高了初始布置。
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公开(公告)号：US6096092A
公开(公告)日：2000-08-01
申请号：US55354
申请日：1998-04-06
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Logic circuits are experimentally automatically synthesized, and a representative line length of each fanout number is estimated on the basis of a net list resulting from the synthesis. The representative line length corresponds to a length of a line positioned at a center when plural lines are aligned in the order of their lengths (namely, a median line length WLmed(fn)). Furthermore, a standard deviation .sigma.med(fn) and a probability coefficient K(fn) of the deviation are calculated with regard to each fanout number on the basis of the net list. Then, a defined line length WL(fn) of each fanout number fn is calculated by using an expression, WL(fn) =WLmed(fn)+K(fn).multidot..sigma.med(fn). At this point, when there is a demand for design of an LSI having a high operation speed, the probability coefficient K(fn) is set at a small value, and when there is a demand for design of an LSI completed in a short period of time, the probability coefficient K(fn) is set at a large value. Then, by using a virtual wiring model including the defined line length WL(fn), the logic circuits are automatically synthesized, and a net list resulting from the synthesis is used for generating a layout of the logic circuits.
摘要翻译： 逻辑电路被实验地自动合成，并且基于从合成得到的网络列表来估计每个扇出数的代表性线路长度。 代表线长度对应于当多个线以其长度的顺序对准时（即，中间线长度WLmed（fn）））的位于中心的线的长度。 此外，基于净列表，针对每个扇出数计算偏差的标准偏差σmed（fn）和概率系数K（fn）。 然后，通过使用表达式WL（fn）= WLmed（fn）+ K（fn）x sigma med（fn）来计算每个扇出数fn的限定行长度WL（fn）。 此时，当需要具有高操作速度的LSI的设计时，将概率系数K（fn）设定为较小的值，并且当需要短时间内完成的LSI的设计时 的时间，将概率系数K（fn）设定为较大的值。 然后，通过使用包含定义的线长度WL（fn）的虚拟布线模型，逻辑电路被自动合成，并且由合成产生的网络列表用于生成逻辑电路的布局。
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公开(公告)号：US5187668A
公开(公告)日：1993-02-16
申请号：US621893
申请日：1990-12-04
申请人： Hiroaki Okude , Masahiko Toyonaga , Toshiro Akino
发明人： Hiroaki Okude , Masahiko Toyonaga , Toshiro Akino
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： There is provided a placement optimization system for determining layout in printed circuits and semiconductor substrates, comprising input means for inputting circuit connection information, placement optimization means for deriving wiring density distribution on the basis of the circuit connection information, evaluating the height and/or width of the wiring region statistically estimated from the wiring density distribution, and output means for outputting the resultant placement position information. Further, the placement optimization system may comprise means for collecting placement elements into sets, determining placement of the sets, then developing the sets into elements, and determining optimum placement positions of the elements.
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公开(公告)号：US5272645A
公开(公告)日：1993-12-21
申请号：US704181
申请日：1991-05-22
CPC分类号： G06F17/5077
摘要： A plurality of wires are effectively laid in a channel having a plurality of wiring layers and sandwiched between two rows of terminals. In order to complete channel routing, horizontal segments of the wires are initially generated. The horizontal segments are then allocated on at least one imaginary segment generated on each layer contained in the channel. The imaginary segment is in parallel with the rows of terminals in the channel. The horizontal segments are bent for reduction of the channel height based on design rules for each layer. Finally, vertical segments of the wires are generated.
摘要翻译： 多条电线被有效地铺设在具有多个布线层并夹在两排端子之间的通道中。 为了完成通道路由，最初生成线的水平段。 然后将水平段分配在在通道中包含的每个层上生成的至少一个虚拟段上。 虚部与通道中的各行终端平行。 根据每层的设计规则，水平段被弯曲以减少通道高度。 最后，生成线的垂直段。
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公开(公告)号：US20050289499A1
公开(公告)日：2005-12-29
申请号：US11159291
申请日：2005-06-23
申请人： Osamu Ogawa , Dai Hattori , Keiichi Kurokawa , Masahiko Toyonaga
发明人： Osamu Ogawa , Dai Hattori , Keiichi Kurokawa , Masahiko Toyonaga
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A CDFG which is a graph representing calculations and a data flow included in the design specifications of a circuit is generated S101, a clock cycle required for the processing is obtained and thus an allocated resource connection graph is generated S102. When the allocated resource connection graph includes nodes to which hardware resources having the same function are allocated, a sharing edge for controlling sharing of the nodes is added between the nodes S103. A provisional layout of the allocated resource connection graph having the sharing edge added thereto is provided S104, and the nodes of the allocated resource connection graph are shared based on the layout result S105. The sharing edge is provided with attribute or weight such as attraction or repulsion. Thus, the distance between the nodes in the layout result is controlled and the degree at which the resources are shared is controlled.
摘要翻译： 产生表示电路设计规范中的计算和数据流的曲线图CD1G，获得处理所需的时钟周期，从而生成分配的资源连接图。当分配的资源 连接图包括分配了具有相同功能的硬件资源的节点，在节点S103之间添加用于控制节点共享的共享边。提供具有添加了共享边的已分配资源连接图的临时布局S 104，并且基于布局结果S 105共享所分配的资源连接图的节点。共享边缘被赋予诸如吸引力或排斥性的属性或权重。 因此，控制布局结果中的节点之间的距离，并且控制资源共享的程度。
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