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公开(公告)号：US5490083A
公开(公告)日：1996-02-06
申请号：US130385
申请日：1993-10-01
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5045
摘要： The logic elements and net list contained in a logic circuit are inputted to an electronic calculator. The total number N1 of primary adjacent logic circuits which are connected directly to all the logic elements contained in the foregoing logic circuit, respectively is calculated from the inputted logic elements and net list. The total number N2 of primary and secondary adjacent logic circuits, which is the sum of the foregoing total number N1 of primary adjacent logic circuits and the total number of secondary adjacent logic circuits which are connected directly to the primary adjacent logic circuits, respectively, is calculated from the inputted logic elements and net list. The difference between the logarithmic value of the foregoing total number N1 of primary adjacent logic circuits and the logarithmic value of the foregoing total number N2 of primary and secondary adjacent logic circuits is calculated as a value for classification which characterizes the aforesaid logic circuit.
摘要翻译： 包含在逻辑电路中的逻辑元件和网络列表被输入到电子计算器。 从输入的逻辑元件和网络列表中分别计算直接连接到上述逻辑电路中包含的所有逻辑元件的主相邻逻辑电路的总数N1。 主相邻逻辑电路的总数N2是主相邻逻辑电路的前述总数N1和直接连接到主相邻逻辑电路的次相邻逻辑电路的总数之和，分别为 从输入的逻辑元素和网络列表中计算。 主相邻逻辑电路的前述总数N1的对数值与初级和次级相邻逻辑电路的前述总数N2的对数值之间的差被计算为表征上述逻辑电路的分类值。
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2.发明授权Method for automating top-down design processing for the design of LSI functions and LSI mask layouts 失效自动设计LSI功能和LSI面板布局的自顶向下设计处理方法
公开(公告)号：US5963730A
公开(公告)日：1999-10-05
申请号：US717670
申请日：1996-09-23
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5072
摘要： A netlist between functional macros is entered. Based on the netlist, an outline layout process for a functional macro is performed and physical specifications for the functional macro are determined from an outline layout produced by the outline layout process. Thereafter, a logic synthesis process is performed on the basis of the physical specifications determined. Based on the outline layout, a logic, obtained by the logic synthesis, is laid out. This makes it possible to reduce the number of times a circuit synthesis process is redone, taking into account a laying-out at an upper-stage functional design process in which no gate level is specified. For this reason, an improved LSI automatic design method is provided which is able to complete an LSI layout design, in which the LSI area and the LSI delay value are optimized, in a short period of time.
摘要翻译： 输入功能宏之间的网表。 基于网表，执行用于功能宏的轮廓布局处理，并且根据由轮廓布局处理产生的轮廓布局来确定功能宏的物理规格。 此后，基于所确定的物理规格执行逻辑合成处理。 基于大纲布局，通过逻辑综合得到逻辑。 这使得可以减少电路合成过程被重做的次数，同时考虑到在没有指定门级的上级功能设计过程中的布局。 因此，提供了一种改进的LSI自动设计方法，其能够在短时间内完成LSI面积和LSI延迟值被优化的LSI布局设计。
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公开(公告)号：US5673200A
公开(公告)日：1997-09-30
申请号：US667284
申请日：1996-06-20
CPC分类号： G06F17/505
摘要： In synthesizing a gate level logic circuit using a computer based on behavioral description of LSI, a logic circuit is first synthesized based on the behavioral description and, then, its power consumption is obtained from the total number of operations. Thereafter, a specific signal propagation path having a larger power consumption is found out from a plurality of signal propagation paths in the logic circuit. A partial logic circuit consisting of logic elements positioned on the specific signal propagation path is optimized in the number of level, thereby creating an optimized partial circuit. Thereafter, obtained is a power consumption of a logic circuit consisting of the optimized partial circuit and the remaining circuit other than the circuit portion optimized. When thus obtained power consumption is small, the partial circuit being not optimized is replaced by the above optimized partial circuit. Accordingly, it becomes possible to reduce overall power consumption while adequately maintaining an area and speed performance of the logic circuit.
摘要翻译： 在使用基于LSI的行为描述的计算机合成门级逻辑电路时，首先基于行为描述合成逻辑电路，然后从总操作数获得其功耗。 此后，从逻辑电路中的多个信号传播路径中找出具有较大功耗的特定信号传播路径。 由位于特定信号传播路径上的逻辑元件组成的部分逻辑电路在电平数量上被优化，从而产生优化的部分电路。 此后，获得的是由优化的部分电路和除优化的电路部分之外的剩余电路组成的逻辑电路的功耗。 当这样获得的功耗小时，未优化的部分电路被上述优化的部分电路所取代。 因此，可以在充分维持逻辑电路的面积和速度性能的同时降低总体功耗。
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4.发明授权Clock distribution circuit with clock branch circuits connected to outgoing and return lines and outputting synchronized clock signals by summing time integrals of clock signals on the outgoing and return lines 失效时钟分配电路，其时钟分支电路连接到输出和返回线，并通过对输出和返回线上的时钟信号的时间积分求和来输出同步时钟信号
公开(公告)号：US5896055A
公开(公告)日：1999-04-20
申请号：US755817
申请日：1996-11-26
CPC分类号： G06F1/10
摘要： A layout area includes a clock interconnection consisting of an upward interconnection and a downward interconnection. The upward interconnection extends from the output terminal of a clock buffer which receives an external clock signal to a turning point while passing along the vicinity of a plurality of flip-flops. The downward interconnection extends from the turning point to a free end, reversing along the upward interconnection. Clock branch circuits are provided in the vicinity of the flip-flops. The clock branch circuits have a function of letting a third clock signal make a transition when the sum of the time integral of a first clock signal on the upward interconnection and the time integral of a second clock signal on the downward interconnection has become equal to the time integral for one pulse of one of the first clock signal and the second clock signal.
摘要翻译： 布局区域包括由向上互连和向下互连组成的时钟互连。 向上互连从时钟缓冲器的输出端子延伸，该时钟缓冲器在沿着多个触发器的附近通过时接收外部时钟信号到转折点。 向下的互连从转折点延伸到自由端，沿着向上的互连方向反转。 在触发器附近提供时钟分支电路。 时钟分支电路具有使第三时钟信号在向上互连上的第一时钟信号的时间积分与下行互连上的第二时钟信号的时间积分的和与 第一时钟信号和第二时钟信号之一的一个脉冲的时间积分。
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5.发明授权Method and apparatus for automatically arranging circuit elements in data-path circuit 失效用于在数据路径电路中自动布置电路元件的方法和装置
公开(公告)号：US5657243A
公开(公告)日：1997-08-12
申请号：US510673
申请日：1995-08-03
CPC分类号： G06F17/5068
摘要： An automatic layout of a data-path circuit, whose performance and area are optimized, requires to input a data-path circuit, produce an external terminal directive branch having a start point placed on an input terminal group of the data-path circuit and an end point placed on an output terminal group of the same, and produce in-circuit directive branches corresponding to respective connecting lines between two circuit elements in the data-path circuit, each in-circuit directive branch having a start point placed on one circuit element supplying a signal to a related connecting line and an end point placed on the other circuit element receiving the signal from the same connecting line. Subsequently, a group circuit is produced based on the relationship between the in-circuit directive branches and the circuit elements, the group circuit comprising a plurality of circuit elements performing a series of logic processing per 1-bit signal. A layout evaluation is then produced so as to comprise an evaluation satisfying a requirement that a direction of the external terminal directive branch is met with directions of the in-circuit directive branches. Thereafter, the layout of circuit elements is optimized based on the layout evaluation and the resultant layout is outputted.
摘要翻译： 数据路径电路的自动布局，其性能和面积被优化，需要输入数据路径电路，产生具有放置在数据路径电路的输入端子组上的起始点的外部终端指令分支，以及 终端放置在其输出端子组上，并且产生与数据通路电路中的两个电路元件之间的相应连接线相对应的在线指向分支，每个在线指向分支具有放置在一个电路元件上的起始点 向相关的连接线提供信号，并将另一个电路元件上的终点提供在从相同的连接线接收信号的位置上。 随后，基于在线指令分支和电路元件之间的关系产生组电路，组电路包括对每1位信号执行一系列逻辑处理的多个电路元件。 然后产生布局评估，以便包括满足外部终端指令分支的方向满足在线指令分支的指示的要求的评估。 此后，基于布局评估优化电路元件的布局，并输出结果布局。
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公开(公告)号：US06961913B1
公开(公告)日：2005-11-01
申请号：US10130546
申请日：2000-11-08
申请人： Kaoru Okazaki , Masanobu Mizuno , Michiaki Muraoka
发明人： Kaoru Okazaki , Masanobu Mizuno , Michiaki Muraoka
CPC分类号： G06F17/5045
摘要： An IP database includes a system level IP used in system level design. IPs A and B in the system level IP are divided into processing algorithm description portions, input data structure definition portions and output data structure definition portions. When a communication channel is provided between the IPs communicating data in architecture or functional design, a conversion circuit generating means generates a data conversion circuit between the communication channel and each of the IPs with reference to the IP database.
摘要翻译： IP数据库包括系统级设计中使用的系统级IP。 系统级IP中的IP A和B分为处理算法描述部分，输入数据结构定义部分和输出数据结构定义部分。 当在通过体系结构或功能设计中传送数据的IP之间提供通信信道时，转换电路产生装置参考IP数据库在通信信道和每个IP之间生成数据转换电路。
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公开(公告)号：US20050149897A1
公开(公告)日：2005-07-07
申请号：US10766955
申请日：2004-01-30
申请人： Hiroyuki Yamashita , Takao Shinsha , Hideaki Fujikake , Toshiaki Kowatari , Tomoya Hirao , Atsushi Ohkuma , Hiroaki Nishi , Michiaki Muraoka
发明人： Hiroyuki Yamashita , Takao Shinsha , Hideaki Fujikake , Toshiaki Kowatari , Tomoya Hirao , Atsushi Ohkuma , Hiroaki Nishi , Michiaki Muraoka
IPC分类号： G06F11/28 , G01R31/3183 , G06F17/50
CPC分类号： G06F17/5022 , G01R31/318314 , G06F2217/86
摘要： A hardware/software co-verification method that achieves fast simulation execution by implementing a C-based native code simulation without degrading the accuracy of timing verification. This method is a method for co-verifying hardware and software, by using a host CPU, for a semiconductor device on which at least one target CPU and one OS are mounted wherein, first, a timed software component described in a C-based language or constructed from binary code native to the host CPU and a hardware component described in the C-based language are input as verification models, necessary compiling is performed, and the compiled components are linked together. Next, a testbench is input and compiled. Then, the components and the testbench are linked together, after which simulation is performed and the result of the simulation is output.
摘要翻译： 一种通过实现基于C的本地代码模拟实现快速仿真执行的硬件/软件协同验证方法，而不会降低定时验证的准确性。 该方法是用于通过使用主机CPU对安装至少一个目标CPU和一个OS的半导体器件来共同验证硬件和软件的方法，其中首先，以基于C的语言描述的定时软件组件 或者由主机CPU本机的二进制代码构成，并将基于C语言描述的硬件组件输入作为验证模型，执行必要的编译，并将已编译的组件链接在一起。 接下来，输入和编译测试台。 然后，将组件和测试台连接在一起，然后进行仿真并输出仿真结果。
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8.发明授权公开(公告)号：US07155690B2
公开(公告)日：2006-12-26
申请号：US10766955
申请日：2004-01-30
申请人： Hiroyuki Yamashita , Takao Shinsha , Hideaki Fujikake , Toshiaki Kowatari , Tomoya Hirao , Atsushi Ohkuma , Hiroaki Nishi , Michiaki Muraoka
发明人： Hiroyuki Yamashita , Takao Shinsha , Hideaki Fujikake , Toshiaki Kowatari , Tomoya Hirao , Atsushi Ohkuma , Hiroaki Nishi , Michiaki Muraoka
CPC分类号： G06F17/5022 , G01R31/318314 , G06F2217/86
摘要： A hardware/software co-verification method that achieves fast simulation execution by implementing a C-based native code simulation without degrading the accuracy of timing verification. This method is a method for co-verifying hardware and software, by using a host CPU, for a semiconductor device on which at least one target CPU and one OS are mounted wherein, first, a timed software component described in a C-based language or constructed from binary code native to the host CPU and a hardware component described in the C-based language are input as verification models, necessary compiling is performed, and the compiled components are linked together. Next, a testbench is input and compiled. Then, the components and the testbench are linked together, after which simulation is performed and the result of the simulation is output.
摘要翻译： 一种通过实现基于C的本地代码模拟实现快速仿真执行的硬件/软件协同验证方法，而不会降低定时验证的准确性。 该方法是用于通过使用主机CPU对安装至少一个目标CPU和一个OS的半导体器件来共同验证硬件和软件的方法，其中首先，以基于C的语言描述的定时软件组件 或者由主机CPU本机的二进制代码构成，并将基于C语言描述的硬件组件输入作为验证模型，执行必要的编译，并将已编译的组件链接在一起。 接下来，输入和编译测试台。 然后，将组件和测试台连接在一起，然后进行仿真并输出仿真结果。
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公开(公告)号：US20060036974A1
公开(公告)日：2006-02-16
申请号：US11211512
申请日：2005-08-26
申请人： Kaoru Okazaki , Masanobu Mizuno , Michiaki Muraoka
发明人： Kaoru Okazaki , Masanobu Mizuno , Michiaki Muraoka
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： An IP database includes a system level IP used in system level design. IPs A and B in the system level IP are divided into processing algorithm description portions, input data structure definition portions and output data structure definition portions. When a communication channel is provided between the IPs communicating data in architecture or functional design, a conversion circuit generating means generates a data conversion circuit between the communication channel and each of the IPs with reference to the IP database.
摘要翻译： IP数据库包括系统级设计中使用的系统级IP。 系统级IP中的IP A和B分为处理算法描述部分，输入数据结构定义部分和输出数据结构定义部分。 当在通过体系结构或功能设计中传送数据的IP之间提供通信信道时，转换电路产生装置参考IP数据库在通信信道和每个IP之间生成数据转换电路。
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10.发明授权Database for designing integrated circuit device, and method for designing integrated circuit device 有权集成电路器件设计数据库，集成电路器件设计方法公开(公告)号：US06526561B2
公开(公告)日：2003-02-25
申请号：US09418311
申请日：1999-10-14
IPC分类号： G06F1750
CPC分类号： G06F17/5022 , G06F17/5045
摘要： A database, in which data is stored in a flexibly usable state, is provided for use in the design of an integrated circuit device, and a method for designing an integrated circuit device using such a database is also provided. A design environment includes: a virtual core database (VCDB), which is hierarchical design data storage; and a virtual core database management system (VCDBMS) as a control system. The VCDB includes architecture information and a VC cluster. The VC cluster includes: a specification VC for storing therein data at a specification level; an architecture VC for storing therein data at an architectural level; an RTL-VC for storing therein data at a register transfer level; and a performance index used for evaluating the performance of the respective VCs. By providing these VCs for respective layers, new VCs can be generated, data within the VCs can be modified and instances can be generated at the respective levels. As a result, the data can be used flexibly and recycled as well.
摘要翻译： 提供数据库，其中以可灵活使用的状态存储数据，用于集成电路设备的设计，并且还提供了使用这种数据库来设计集成电路装置的方法。 设计环境包括：虚拟核心数据库（VCDB），是分层设计数据存储; 和虚拟核心数据库管理系统（VCDBMS）作为控制系统。 VCDB包括架构信息和VC集群。 VC集群包括：用于在其中存储规范级别的数据的规范VC; 用于在架构级存储数据的架构VC; 用于在寄存器传送级别存储数据的RTL-VC; 以及用于评估各个VC的性能的性能指标。 通过为各层提供这些VC，可以生成新的VC，可以修改VC内的数据，并且可以在各个级别生成实例。 因此，数据可以灵活使用，并可循环使用。
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