公开(公告)号：US20120133407A1

公开(公告)日：2012-05-31

申请号：US13292133

申请日：2011-11-09

申请人： Masanao YOKOYAMA ,  Noboru OKUZONO

发明人： Masanao YOKOYAMA ,  Noboru OKUZONO

IPC分类号： H03K3/037

CPC分类号： G09G3/3611 ,  G09G2310/0264 ,  G09G2310/08 ,  H03K3/012 ,  H03K3/356156 ,  H03K3/35625

摘要： An input buffer chooses, in accordance with first control clocks, to output an input data signal or output a high-impedance signal. A master flip-flop chooses, in accordance with second control clocks, to output a data signal received from the input buffer or retain a currently output data signal. A master-slave switch chooses, in accordance with the second control clocks, to output a high-impedance signal or output a data signal received from the master flip-flop. A slave flip-flop chooses, in accordance with the second control clocks, to retain a currently output data signal or output a data signal received from the master-slave switch. A clock buffer inputs the second control clocks, and generates and outputs the first control clocks.

摘要翻译： 输入缓冲器根据第一控制时钟选择输出输入数据信号或输出高阻抗信号。 主触发器根据第二控制时钟选择输出从输入缓冲器接收的数据信号或保持当前输出的数据信号。 主从开关根据第二控制时钟选择输出高阻抗信号或输出从主触发器接收的数据信号。 从触发器根据第二控制时钟选择保持当前输出的数据信号或输出从主从交换机接收的数据信号。 时钟缓冲器输入第二控制时钟，并产生并输出第一控制时钟。