公开(公告)号：US08737541B2

公开(公告)日：2014-05-27

申请号：US13501189

申请日：2010-10-12

申请人： Nobuyuki Tanaka ,  Masao Orio

发明人： Nobuyuki Tanaka ,  Masao Orio

IPC分类号： H04L27/06

CPC分类号： H03M13/451 ,  H03M13/6525 ,  H04L1/0045

摘要： Provided is a decoding apparatus capable of reducing the error rate of the decoding results and also the circuit scale. A computing unit computes a plurality of distances only for a number of code word candidates of code words from demodulated data, the number being smaller than a number of values the code words can express, the code words having a possibility of being transmitted. A decoding unit decodes the code words from the plurality of computed distances. This invention is applicable to a decoding apparatus for Long Term Evolution (LTE).

摘要翻译： 提供了能够降低解码结果的错误率以及电路规模的解码装置。 计算单元仅对来自解调数据的码字的多个码字候选计算多个距离，该数字小于码字可以表达的值的数量，具有被发送的可能性的码字。 解码单元从多个计算距离中解码码字。 本发明适用于长期演进（LTE）的解码装置。

公开(公告)号：US08370713B2

公开(公告)日：2013-02-05

申请号：US13111557

申请日：2011-05-19

申请人： Masao Orio

发明人： Masao Orio

IPC分类号： G11C29/00

CPC分类号： H03M13/2957 ,  H03M13/6561 ,  H03M13/6566 ,  H04L1/005 ,  H04L1/0052 ,  H04L1/0066

摘要： An error correction code decoding device comprises a first memory having a memory space like a matrix, a first decoding unit writing a first information into the first memory along a first direction, a second decoding unit reading the first information from the first memory along a second direction and a plurality of turbo decoders included in the second decoding unit, and differentiating access timing to a same row or same column with each other.

摘要翻译： 纠错码解码装置包括具有像矩阵的存储器空间的第一存储器，第一解码单元沿着第一方向将第一信息写入第一存储器，第二解码单元沿着第二存储器从第一存储器读取第一信息 方向和包括在第二解码单元中的多个turbo解码器，并且将访问定时与彼此相同的列或相同列区分开。

公开(公告)号：US08201052B2

公开(公告)日：2012-06-12

申请号：US12285751

申请日：2008-10-14

申请人： Masao Orio ,  Mitsunori Takanashi

发明人： Masao Orio ,  Mitsunori Takanashi

IPC分类号： G11C29/00

CPC分类号： H04L1/0054 ,  H03M13/2957 ,  H03M13/3994 ,  H03M13/41 ,  H04L1/0078

摘要： For the coded data that was transmitted via a communication channel, a known code portion thereof that is a code portion corresponding to known data is detected. When the known code portion is not detected from the coded data, the coded data will be decoded. When the known code portion is detected from the coded data, at least a part thereof will be replaced with normal data, and the decoding will be performed on the coded data after the substitution.

摘要翻译： 对于通过通信信道发送的编码数据，检测作为对应于已知数据的代码部分的已知代码部分。 当从编码数据未检测出已知码部分时，编码数据将被解码。 当从编码数据中检测到已知代码部分时，至少其一部分将被正常数据替换，并且将在替换之后对编码数据进行解码。

公开(公告)号：US08010867B2

公开(公告)日：2011-08-30

申请号：US11870586

申请日：2007-10-11

申请人： Masao Orio

发明人： Masao Orio

IPC分类号： H03M13/00

CPC分类号： H03M13/2957 ,  H03M13/6561 ,  H03M13/6566 ,  H04L1/005 ,  H04L1/0052 ,  H04L1/0066

摘要： An error correction code decoding device comprises a first memory having a memory space like a matrix, a first decoding unit writing a first information into the first memory along a first direction, a second decoding unit reading the first information from the first memory along a second direction and a plurality of turbo decoders included in the second decoding unit, and differentiating access timing to a same row or same column with each other.

摘要翻译： 纠错码解码装置包括具有像矩阵的存储器空间的第一存储器，第一解码单元沿着第一方向将第一信息写入第一存储器，第二解码单元沿着第二存储器从第一存储器读取第一信息 方向和包括在第二解码单元中的多个turbo解码器，并且将访问定时与彼此相同的列或相同列区分开。

公开(公告)号：US07467347B2

公开(公告)日：2008-12-16

申请号：US10641563

申请日：2003-08-15

申请人： Masao Orio

发明人： Masao Orio

IPC分类号： H03M13/41

CPC分类号： H04L1/005 ,  G11B20/18 ,  H03M13/2957 ,  H03M13/3723 ,  H03M13/3905 ,  H03M13/3972 ,  H03M13/658 ,  H04L1/0054 ,  H04L1/0055 ,  H04L1/006 ,  H04L1/0066

摘要： A decoding method is provided which is capable of achieving decoding of error correcting codes in a simple configuration and in a short time. In the method of decoding error correcting codes to perform iterative decoding which consists of forward processing, backward processing, and extrinsic information value calculating, a backward processing path metric value obtained in the previous decoding iteration for a window boundary is used as an initial value of the backward processing path metric value for the window boundary in the next decoding iteration.

摘要翻译： 提供一种解码方法，其能够以简单的配置和短时间来实现纠错码的解码。 在解码纠错码进行正向处理，后向处理和外在信息值计算的迭代解码的方法中，使用在前一个窗口边界的解码迭代中获得的后向处理路径量度值作为初始值 在下一个解码迭代中窗口边界的后向处理路径度量值。

公开(公告)号：US20080092028A1

公开(公告)日：2008-04-17

申请号：US11907588

申请日：2007-10-15

申请人： Masao Orio

发明人： Masao Orio

IPC分类号： H03M13/37 ,  G06F11/07

CPC分类号： H03M13/3911 ,  H03M13/2957 ,  H03M13/658

摘要： A decoding device includes a BM calculator calculating a branch metric in a Log-MAP algorithm from received data and extrinsic information, an ACS operator calculating a maximum value of a path metric based on the branch metric, a correction term calculator calculating a Jacobian correction value of the path metric, and a correction operator correcting the path metric by adjusting a value of the Jacobian correction value based on a size of the received data and adding the adjusted correction value to the maximum value.

摘要翻译： 解码装置包括：BM计算器，从接收到的数据和外部信息计算Log-MAP算法中的分支度量; ACS算子，基于分支量度计算路径度量的最大值;校正项计算器，计算雅可比校正值 以及校正运算符，通过基于接收到的数据的大小调整雅可比校正值的值来校正路径度量，并将调整后的校正值加到最大值。

公开(公告)号：US20070124657A1

公开(公告)日：2007-05-31

申请号：US11590823

申请日：2006-11-01

申请人： Masao Orio

发明人： Masao Orio

IPC分类号： H03M13/03

CPC分类号： H03M13/2975 ,  H03M13/3753 ,  H03M13/39 ,  H04L1/0051

摘要： A decoding apparatus includes a first decoder and a second decoder performing iterative decoding on each of a plurality of code blocks, each as a decoding unit, contained in a transport block, and a stop/end determination section determining whether or not to stop iterative decoding based on an output result from the second decoder. The stop/end determination section determines whether or not to stop the iterative decoding on each code block based on a determination result on whether error correction of iterative decoding in each code block is converted or not, and further determines whether or not to stop the iterative decoding of the transfer block based on the determination result in each code block. If it is determined that error correction of iterative decoding is not converted in one code block, the decoding process of the transport block containing the relevant code block is stopped.

摘要翻译： 解码装置包括第一解码器和第二解码器，对包含在传输块中的每个作为解码单元的多个码块中的每一个执行迭代解码，以及停止/结束确定部分，确定是否停止迭代解码 基于来自第二解码器的输出结果。 停止/结束确定部分基于关于每个代码块中的迭代解码的纠错是否被转换的确定结果来确定是否停止对每个代码块的迭代解码，并进一步确定是否停止迭代 基于每个代码块中的确定结果对传送块进行解码。 如果确定迭代解码的纠错不在一个码块中转换，则包含相关码块的传输块的解码处理被停止。

公开(公告)号：US07992073B2

公开(公告)日：2011-08-02

申请号：US11590823

申请日：2006-11-01

申请人： Masao Orio

发明人： Masao Orio

IPC分类号： H03M13/00

CPC分类号： H03M13/2975 ,  H03M13/3753 ,  H03M13/39 ,  H04L1/0051

摘要： A decoding apparatus includes a first decoder and a second decoder performing iterative decoding on each of a plurality of code blocks, each as a decoding unit, contained in a transport block, and a stop/end determination section determining whether or not to stop iterative decoding based on an output result from the second decoder. The stop/end determination section determines whether or not to stop the iterative decoding on each code block based on a determination result on whether error correction of iterative decoding in each code block is converted or not, and further determines whether or not to stop the iterative decoding of the transfer block based on the determination result in each code block. If it is determined that error correction of iterative decoding is not converted in one code block, the decoding process of the transport block containing the relevant code block is stopped.

摘要翻译： 解码装置包括第一解码器和第二解码器，对包含在传输块中的每个作为解码单元的多个码块中的每一个执行迭代解码，以及停止/结束确定部分，确定是否停止迭代解码 基于来自第二解码器的输出结果。 停止/结束确定部分基于关于每个代码块中的迭代解码的纠错是否被转换的确定结果来确定是否停止对每个代码块的迭代解码，并进一步确定是否停止迭代 基于每个代码块中的确定结果对传送块进行解码。 如果确定迭代解码的纠错不在一个码块中转换，则包含相关码块的传输块的解码处理被停止。

公开(公告)号：US07913153B2

公开(公告)日：2011-03-22

申请号：US11634957

申请日：2006-12-07

申请人： Masao Orio

发明人： Masao Orio

IPC分类号： H03M13/00

CPC分类号： H04L1/0055 ,  G06F7/4833 ,  H03M13/2957 ,  H03M13/3905 ,  H03M13/3911

摘要： An arithmetic circuit includes a NOR circuit for outputting 1-bit inverted logical OR sf from all of a first bit group x(6) to x(10) containing 0 or more high-order bit of a path metric value composed of a plurality of bits, an inverter for inverting each bit of a second bit group x(2) to x(5) and outputting a third bit group rs(0) to rs(3), an AND circuit for outputting a fourth bit group ns(0) to ns(3) that contain results of calculating a logical AND of sf and rs(0) to rs(3), and a CF output section for outputting a correction factor CF based on ns(0) to ns(3).

摘要翻译： 运算电路包括：NOR电路，用于从包含多个第一位组x（6）到x（10）的所有第一位组x（10）输出1位反相逻辑OR sf，该第一位组包含由多个 位，反相器，用于将第二位组x（2）的每个位x（5）反相并将第三位组rs（0）输出到rs（3）; AND电路，用于输出第四位组ns（0 ）到包含计算sf和rs（0）到rs（3）的逻辑AND的结果的ns（3），以及用于基于ns（0）至ns（3）输出校正因子CF的CF输出部分。

公开(公告)号：US07886209B2

公开(公告)日：2011-02-08

申请号：US11622780

申请日：2007-01-12

申请人： Masao Orio

发明人： Masao Orio

IPC分类号： H03M13/00

CPC分类号： H03M13/2975

摘要： A decoding apparatus includes a first decoder and a second decoder as a decoding processor for performing iterative decoding on received data, a hard decision section for calculating hard decision results based on logarithmic likelihood ratios L1 and L2 from the first and second decoders, and a stop determination section performing stop determination on whether or not to stop the iterative decoding on the received data based on the result of the hard decision section. The decoding apparatus completes one-time iterative decoding by executing decoding process in each of the first and second decoders. The stop determination section executes stop determination at the timings of completion of the decoding process in the first decoder and completion of the decoding process in the second decoder.

摘要翻译： 解码装置包括第一解码器和第二解码器，作为用于对接收到的数据执行迭代解码的解码处理器，用于基于来自第一和第二解码器的对数似然比L1和L2计算硬判决结果的硬判决部分，以及停止 确定部分基于硬判决部分的结果，执行是否停止对接收到的数据的迭代解码的停止确定。 解码装置通过在第一和第二解码器中的每一个执行解码处理来完成一次迭代解码。 停止判定部在第一解码器中的解码处理完成的定时和第二解码器中的解码处理的完成中执行停止判定。