公开(公告)号：US20170300330A1

公开(公告)日：2017-10-19

申请号：US14476848

申请日：2014-09-04

Applicant: Massachusetts Institute of Technology

Inventor： David Joseph Whelihan ,  Paul Stanton Keltcher

IPC: G06F9/30 ,  G06F12/14 ,  G06F15/80

CPC classification number: G06F9/30087 ,  G06F9/3009 ,  G06F9/52 ,  G06F12/1425 ,  G06F15/80 ,  G06F2212/1052

Abstract: Global synchrony changes the way computers can be programmed. A new class of ISA level instructions (the globally-synchronous load-store) of the present invention is presented. In the context of multiple load-store machines, the globally synchronous load-store architecture allows the programmer to think about a collection of independent load-store machines as a single load-store machine. These ISA instructions may be applied to a distributed matrix transpose or other data that exhibit a high degree of data non-locality and difficulty in efficiently parallelizing on modern computer system architectures. Included in the new ISA instructions are a setup instruction and a synchronous coalescing access instruction (“sca”). The setup instruction configures a head processor to set up a global map that corresponds processor data contiguously to the memory. The “sca” instruction configures processors to block processor threads until respective times on a global clock, derived from the global map, to access the memory.

公开(公告)号：US10255070B2

公开(公告)日：2019-04-09

申请号：US14476848

申请日：2014-09-04

Applicant: Massachusetts Institute of Technology

Inventor： David Joseph Whelihan ,  Paul Stanton Keltcher

IPC: G06F9/30 ,  G06F9/52 ,  G06F12/14 ,  G06F15/80

Abstract: Global synchrony changes the way computers can be programmed. A new class of ISA level instructions (the globally-synchronous load-store) of the present invention is presented. In the context of multiple load-store machines, the globally synchronous load-store architecture allows the programmer to think about a collection of independent load-store machines as a single load-store machine. These ISA instructions may be applied to a distributed matrix transpose or other data that exhibit a high degree of data non-locality and difficulty in efficiently parallelizing on modern computer system architectures. Included in the new ISA instructions are a setup instruction and a synchronous coalescing access instruction (“sca”). The setup instruction configures a head processor to set up a global map that corresponds processor data contiguously to the memory. The “sca” instruction configures processors to block processor threads until respective times on a global clock, derived from the global map, to access the memory.