公开(公告)号：US20080149991A1

公开(公告)日：2008-06-26

申请号：US11859142

申请日：2007-09-21

申请人： Masumi SAITOH ,  Ken UCHIDA

发明人： Masumi SAITOH ,  Ken UCHIDA

IPC分类号： H01L29/788 ,  H01L21/3205

CPC分类号： H01L29/42324 ,  H01L21/28273 ,  H01L29/165 ,  H01L29/7881

摘要： A non-volatile semiconductor storage device includes: a semiconductor substrate; a source region and a drain region formed in the semiconductor substrate so as to be separated from each other; a first insulating film formed between the source region and the drain region, on the semiconductor substrate; a floating electrode formed on the first insulating film and including a semiconductor conductive material layer having extension strain; a second insulating film formed on the floating electrode; and a control electrode formed on the second insulating film. The extension strain of the floating electrode becomes gradually small as the location advances from the second insulating film toward the first insulating film, and the floating electrode has extension strain of 0.01% or more at an interface between the floating electrode and the second insulating film, and has extension strain less than 0.01% at an interface between the floating electrode and the first insulating film.

摘要翻译： 非易失性半导体存储器件包括：半导体衬底; 源极区域和漏极区域，形成在半导体衬底中以便彼此分离; 在所述半导体衬底上形成在所述源极区域和所述漏极区域之间的第一绝缘膜; 形成在所述第一绝缘膜上并具有延伸应变的半导体导电材料层的浮动电极; 形成在浮置电极上的第二绝缘膜; 以及形成在所述第二绝缘膜上的控制电极。 浮动电极的延伸应变随着位置从第二绝缘膜向第一绝缘膜前进而逐渐变小，浮动电极在浮动电极和第二绝缘膜之间的界面具有0.01％以上的延伸应变， 并且在浮动电极和第一绝缘膜之间的界面处具有小于0.01％的延伸应变。

公开(公告)号：US20120037994A1

公开(公告)日：2012-02-16

申请号：US13283264

申请日：2011-10-27

申请人： Masumi SAITOH ,  Ken UCHIDA

发明人： Masumi SAITOH ,  Ken UCHIDA

IPC分类号： H01L27/092

CPC分类号： H01L29/785 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7843

摘要： A FinFET and nanowire transistor with strain direction optimized in accordance with the sideface orientation and carrier polarity and an SMT-introduced manufacturing method for achieving the same are provided. A semiconductor device includes a pMISFET having a semiconductor substrate, a rectangular solid-shaped semiconductor layer formed at upper part of the substrate to have a top surface parallel to a principal plane of the substrate and a sideface with a (100) plane perpendicular to the substrate's principal plane, a channel region formed in the rectangular semiconductor layer, a gate insulating film formed at least on the sideface of the rectangular layer, a gate electrode on the gate insulator film, and source/drain regions formed in the rectangular semiconductor layer to interpose the channel region therebetween. The channel region is applied a compressive strain in the perpendicular direction to the substrate principal plane. A manufacturing method of the device is also disclosed.

摘要翻译： 提供了根据侧面取向和载流子极性优化的应变方向的FinFET和纳米线晶体管以及用于实现其的SMT引入制造方法。 半导体器件包括具有半导体衬底的pMISFET，形成在衬底上部的矩形固体半导体层，具有平行于衬底的主平面的顶表面和垂直于衬底的（100）面的侧面 基板的主平面，形成在矩形半导体层中的沟道区，至少形成在矩形层的侧面上的栅极绝缘膜，栅极绝缘膜上的栅电极和形成在矩形半导体层中的源/漏区， 在其间插入通道区域。 通道区域在与基板主平面垂直的方向上施加压缩应变。 还公开了该装置的制造方法。

公开(公告)号：US20090242990A1

公开(公告)日：2009-10-01

申请号：US12401704

申请日：2009-03-11

申请人： Masumi SAITOH ,  Ken UCHIDA

发明人： Masumi SAITOH ,  Ken UCHIDA

IPC分类号： H01L27/092 ,  H01L21/28 ,  H01L21/20

CPC分类号： H01L29/785 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7843

摘要： A FinFET and nanowire transistor with strain direction optimized in accordance with the sideface orientation and carrier polarity and an SMT-introduced manufacturing method for achieving the same are provided. A semiconductor device includes a pMISFET having a semiconductor substrate, a rectangular solid-shaped semiconductor layer formed at upper part of the substrate to have a top surface parallel to a principal plane of the substrate and a sideface with a (100) plane perpendicular to the substrate's principal plane, a channel region formed in the rectangular semiconductor layer, a gate insulating film formed at least on the sideface of the rectangular layer, a gate electrode on the gate insulator film, and source/drain regions formed in the rectangular semiconductor layer to interpose the channel region therebetween. The channel region is applied a compressive strain in the perpendicular direction to the substrate principal plane. A manufacturing method of the device is also disclosed.

摘要翻译： 提供了根据侧面取向和载流子极性优化的应变方向的FinFET和纳米线晶体管，以及用于实现其的SMT引入制造方法。 半导体器件包括具有半导体衬底的pMISFET，形成在衬底上部的矩形固体半导体层，具有平行于衬底的主平面的顶表面和垂直于衬底的（100）面的侧面 基板的主平面，形成在矩形半导体层中的沟道区，至少形成在矩形层的侧面上的栅极绝缘膜，栅极绝缘膜上的栅电极和形成在矩形半导体层中的源/漏区， 在其间插入通道区域。 通道区域在与基板主平面垂直的方向上施加压缩应变。 还公开了该装置的制造方法。

公开(公告)号：US20090242986A1

公开(公告)日：2009-10-01

申请号：US12210328

申请日：2008-09-15

申请人： Yukio NAKABAYASHI ,  Ken UCHIDA

发明人： Yukio NAKABAYASHI ,  Ken UCHIDA

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/66795 ,  H01L29/785

摘要： A multi-gate field effect transistor includes: a plurality of semiconductor layers arranged in parallel on a substrate; source and drain regions formed in each of the semiconductor layers; channel regions each provided between the source region and the drain region in each of the semiconductor layers; protection films each provided on an upper face of each of the channel regions; gate insulating films each provided on both side faces of each of the channel regions; a plurality of gate electrodes provided on both side faces of each of the channel regions so as to interpose the gate insulating film, provided above the upper face of each of the channel region so as to interpose the protection film, and containing a metal element; a connecting portion connecting upper faces of the gate electrodes; and a gate wire connected to the connecting portion.

摘要翻译： 多栅极场效应晶体管包括：平行布置在衬底上的多个半导体层; 形成在每个半导体层中的源区和漏区; 沟道区域，每个沟道区域设置在每个半导体层中的源极区域和漏极区域之间; 保护膜分别设置在每个通道区域的上表面上; 栅极绝缘膜各自设置在每个沟道区域的两个侧面上; 设置在每个沟道区域的两个侧面上的多个栅电极，以便设置在每个沟道区域的上表面上方的栅极绝缘膜，以便插入保护膜，并且容纳金属元件; 连接所述栅电极的上表面的连接部; 以及连接到连接部分的栅极线。