公开(公告)号：US07947907B2

公开(公告)日：2011-05-24

申请号：US12098895

申请日：2008-04-07

申请人： Matthew Earl Colburn ,  Ricardo Alves Donaton ,  Conal E Murray ,  Satyanarayana Venkata Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thedorus Eduardos Standaert ,  Xiao Hu Liu

发明人： Matthew Earl Colburn ,  Ricardo Alves Donaton ,  Conal E Murray ,  Satyanarayana Venkata Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thedorus Eduardos Standaert ,  Xiao Hu Liu

IPC分类号： H05K1/03

CPC分类号： H01L21/32139 ,  H01L21/0271 ,  H01L21/31144 ,  H01L21/7682

摘要： An electronic structure including a substrate having a having a dielectric layer with at least one metallic interconnect structure within and a dielectric barrier layer above the dielectric layer, and a multi-layer hardmask stack coated with a self-assembled layer, where the self-assembled layer is a pattern of nanoscale and/or microscale voids which are generated into the dielectric barrier layer and into the dielectric layer next to the metallic interconnect structure to create columns in the dielectric barrier layer and dielectric layer therein. Electronics structures prepared with the process are useful to prepare electronics devices, such as computers and the like.

摘要翻译： 一种电子结构，其包括具有介电层的介质层和介电层上方的介电阻挡层中的至少一个金属互连结构的基板，以及涂覆有自组装层的多层硬掩模堆叠，其中自组装 层是纳米尺度和/或微细孔隙的图案，其在介电阻挡层中产生并且进入与金属互连结构相邻的电介质层中，以在其中的介电阻挡层和电介质层中产生柱。 使用该方法制备的电子结构对制备电子设备（例如计算机等）是有用的。