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    Multiprocessor system with multiple concurrent modes of execution
    3.
    发明授权
    Multiprocessor system with multiple concurrent modes of execution 有权
    具有多个并发执行模式的多处理器系统

    公开(公告)号：US08621478B2

    公开(公告)日：2013-12-31

    申请号：US13008502

    申请日：2011-01-18

    申请人： Daniel Ahn ,  Luis H. Ceze ,  Dong Chen ,  Alan Gara ,  Philip Heidelberger ,  Martin Ohmacht

    发明人： Daniel Ahn ,  Luis H. Ceze ,  Dong Chen ,  Alan Gara ,  Philip Heidelberger ,  Martin Ohmacht

    IPC分类号： G06F9/46

    CPC分类号： G06F9/524 ,  G06F12/08

    摘要： A multiprocessor system supports multiple concurrent modes of speculative execution. Speculation identification numbers (IDs) are allocated to speculative threads from a pool of available numbers. The pool is divided into domains, with each domain being assigned to a mode of speculation. Modes of speculation include TM, TLS, and rollback. Allocation of the IDs is carried out with respect to a central state table and using hardware pointers. The IDs are used for writing different versions of speculative results in different ways of a set in a cache memory.

    摘要翻译： 多处理器系统支持多种并发模式的推测执行。 投机标识号（ID）从可用数字池中分配给投机线程。 池被分为域，每个域被分配到一种投机模式。 投机模式包括TM，TLS和回滚。 对于中央状态表并使用硬件指针执行ID的分配。 ID用于以高速缓冲存储器中的集合的不同方式写入不同版本的推测结果。

    MULTIPROCESSOR SYSTEM WITH MULTIPLE CONCURRENT MODES OF EXECUTION
    4.
    发明申请
    MULTIPROCESSOR SYSTEM WITH MULTIPLE CONCURRENT MODES OF EXECUTION 有权
    具有多个并发模式的多处理器系统

    公开(公告)号：US20110219381A1

    公开(公告)日：2011-09-08

    申请号：US13008502

    申请日：2011-01-18

    申请人： Daniel Ahn ,  Luis H. Ceze ,  Dong Chen ,  Alan Gara ,  Philip Heidelberger ,  Martin Ohmacht

    发明人： Daniel Ahn ,  Luis H. Ceze ,  Dong Chen ,  Alan Gara ,  Philip Heidelberger ,  Martin Ohmacht

    IPC分类号： G06F9/46

    CPC分类号： G06F9/524 ,  G06F12/08

    摘要： A multiprocessor system supports multiple concurrent modes of speculative execution. Speculation identification numbers (IDs) are allocated to speculative threads from a pool of available numbers. The pool is divided into domains, with each domain being assigned to a mode of speculation. Modes of speculation include TM, TLS, and rollback. Allocation of the IDs is carried out with respect to a central state table and using hardware pointers. The IDs are used for writing different versions of speculative results in different ways of a set in a cache memory.

    摘要翻译： 多处理器系统支持多种并发模式的推测执行。 投机标识号（ID）从可用数字池中分配给投机线程。 池被分为域，每个域被分配到一种投机模式。 投机模式包括TM，TLS和回滚。 对于中央状态表并使用硬件指针执行ID的分配。 ID用于以高速缓冲存储器中的集合的不同方式写入不同版本的推测结果。

    READER SET ENCODING FOR DIRECTORY OF SHARED CACHE MEMORY IN MULTIPROCESSOR SYSTEM
    5.
    发明申请
    READER SET ENCODING FOR DIRECTORY OF SHARED CACHE MEMORY IN MULTIPROCESSOR SYSTEM 失效
    在多处理器系统中编写共享高速缓存存储器的目录的读写器集

    公开(公告)号：US20110219191A1

    公开(公告)日：2011-09-08

    申请号：US13008583

    申请日：2011-01-18

    申请人： Daniel Ahn ,  Luis H. Ceze ,  Alan Gara ,  Martin Ohmacht ,  Zhuang Xiaotong

    发明人： Daniel Ahn ,  Luis H. Ceze ,  Alan Gara ,  Martin Ohmacht ,  Zhuang Xiaotong

    IPC分类号： G06F12/08

    CPC分类号： G06F9/524 ,  G06F12/08

    摘要： In a parallel processing system with speculative execution, conflict checking occurs in a directory lookup of a cache memory that is shared by all processors. In each case, the same physical memory address will map to the same set of that cache, no matter which processor originated that access. The directory includes a dynamic reader set encoding, indicating what speculative threads have read a particular line. This reader set encoding is used in conflict checking. A bitset encoding is used to specify particular threads that have read the line.

    摘要翻译： 在具有推测性执行的并行处理系统中，冲突检查发生在所有处理器共享的高速缓冲存储器的目录查找中。 在每种情况下，相同的物理内存地址将映射到同一组缓存，无论哪个处理器发起该访问。 该目录包括一个动态阅读器集编码，指示什么推测线程读取了一条特定的行。 这种读写器编码用于冲突检查。 位组编码用于指定已读取行的特定线程。

    Reader set encoding for directory of shared cache memory in multiprocessor system
    6.
    发明授权
    Reader set encoding for directory of shared cache memory in multiprocessor system 失效
    多处理器系统中的共享缓存内存的读取器集编码

    公开(公告)号：US08751748B2

    公开(公告)日：2014-06-10

    申请号：US13008583

    申请日：2011-01-18

    申请人： Daniel Ahn ,  Luis H. Ceze ,  Alan Gara ,  Martin Ohmacht ,  Zhuang Xiaotong

    发明人： Daniel Ahn ,  Luis H. Ceze ,  Alan Gara ,  Martin Ohmacht ,  Zhuang Xiaotong

    IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

    CPC分类号： G06F9/524 ,  G06F12/08

    摘要： In a parallel processing system with speculative execution, conflict checking occurs in a directory lookup of a cache memory that is shared by all processors. In each case, the same physical memory address will map to the same set of that cache, no matter which processor originated that access. The directory includes a dynamic reader set encoding, indicating what speculative threads have read a particular line. This reader set encoding is used in conflict checking. A bitset encoding is used to specify particular threads that have read the line.

    摘要翻译： 在具有推测性执行的并行处理系统中，冲突检查发生在所有处理器共享的高速缓冲存储器的目录查找中。 在每种情况下，相同的物理内存地址将映射到同一组缓存，无论哪个处理器发起该访问。 该目录包括一个动态阅读器集编码，指示什么推测线程读取了一条特定的行。 这种读写器编码用于冲突检查。 位组编码用于指定已读取行的特定线程。

    Deterministic serialization in a transactional memory system based on thread creation order
    7.
    发明授权
    Deterministic serialization in a transactional memory system based on thread creation order 失效
    基于线程创建顺序的事务内存系统中的确定性序列化

    公开(公告)号：US08694997B2

    公开(公告)日：2014-04-08

    申请号：US12334336

    申请日：2008-12-12

    申请人： Luis H. Ceze ,  Mark H. Oskin

    发明人： Luis H. Ceze ,  Mark H. Oskin

    IPC分类号： G06F9/46 ,  G06F13/00

    CPC分类号： G06F9/52 ,  G06F9/463 ,  G06F9/466 ,  G06F9/522 ,  G06F9/544

    摘要： A hardware and/or software facility for controlling the order of operations performed by threads of a multithreaded application on a multiprocessing system is provided. The facility may serialize or selectively-serialize execution of the multithreaded application such that, given the same input to the multithreaded application, the multiprocessing system deterministically interleaves operations, thereby producing the same output each time the multithreaded application is executed. The facility divides the execution of the multithreaded application code into two or more quantum specifying a deterministic number of operations, and the facility specifies a deterministic order in which the threads execute the two or more quantum. The facility may operate together with a transactional memory system. When the facility operates together with a transactional memory system, each quantum is encapsulated in a transaction that, may be executed concurrently with other transactions, and is committed according to the specified deterministic order.

    摘要翻译： 提供了用于控制多线程应用程序的线程在多处理系统上执行的操作顺序的硬件和/或软件设施。 该设施可以串行化或选择性地串行化多线程应用的执行，使得在给多线程应用程序的相同输入时，多处理系统确定性地交织操作，从而在每次执行多线程应用程序时产生相同的输出。 该设施将多线程应用程序代码的执行划分为指定确定性操作数的两个或多个量子，并且该设施指定线程执行两个或更多个量子的确定性顺序。 该设施可以与事务存储系统一起操作。 当设施与事务存储系统一起运行时，每个量子被封装在可以与其他事务同时执行的事务中，并且根据指定的确定性顺序被提交。

    DETERMINISTIC MULTIPROCESSING
    8.
    发明申请
    DETERMINISTIC MULTIPROCESSING 失效
    决定性多媒体

    公开(公告)号：US20090165006A1

    公开(公告)日：2009-06-25

    申请号：US12334336

    申请日：2008-12-12

    申请人： Luis H. Ceze ,  Mark H. Oskin

    发明人： Luis H. Ceze ,  Mark H. Oskin

    IPC分类号： G06F9/46

    CPC分类号： G06F9/52 ,  G06F9/463 ,  G06F9/466 ,  G06F9/522 ,  G06F9/544

    摘要： A hardware and/or software facility for controlling the order of operations performed by threads of a multithreaded application on a multiprocessing system is provided. The facility may serialize or selectively-serialize execution of the multithreaded application such that, given the same input to the multithreaded application, the multiprocessing system deterministically interleaves operations, thereby producing the same output each time the multithreaded application is executed. The facility divides the execution of the multithreaded application code into two or more quantum specifying a deterministic number of operations, and the facility specifies a deterministic order in which the threads execute the two or more quantum. The facility may operate together with a transactional memory system. When the facility operates together with a transactional memory system, each quantum is encapsulated in a transaction that, may be executed concurrently with other transactions, and is committed according to the specified deterministic order.

    摘要翻译： 提供了用于控制多线程应用程序的线程在多处理系统上执行的操作顺序的硬件和/或软件设施。 该设施可以串行化或选择性地串行化多线程应用的执行，使得在给多线程应用程序的相同输入时，多处理系统确定性地交织操作，从而在每次执行多线程应用程序时产生相同的输出。 该设施将多线程应用程序代码的执行划分为指定确定性操作数的两个或多个量子，并且该设施指定线程执行两个或更多个量子的确定性顺序。 该设施可以与事务存储系统一起操作。 当设施与事务存储系统一起运行时，每个量子被封装在可以与其他事务同时执行的事务中，并且根据指定的确定性顺序被提交。

    SYSTEM AND METHOD FOR HANDLING OVERFLOW IN HARDWARE TRANSACTIONAL MEMORY WITH LOCKS
    9.
    发明申请
    SYSTEM AND METHOD FOR HANDLING OVERFLOW IN HARDWARE TRANSACTIONAL MEMORY WITH LOCKS 审中-公开
    在具有锁定的硬件交易存储器中处理溢出的系统和方法

    公开(公告)号：US20090177847A1

    公开(公告)日：2009-07-09

    申请号：US11971511

    申请日：2008-01-09

    申请人： Luis H. Ceze ,  Christoph von Praun

    发明人： Luis H. Ceze ,  Christoph von Praun

    IPC分类号： G06F12/00

    CPC分类号： G06F9/466 ,  G06F9/526

    摘要： A system, method and computer program product for processing overflow transactions in a transactional memory system. The transactional memory system is provided in a multiprocessing system having one or more processor devices and a shared memory storage system, and implements a best effort hardware transactional memory system. The method includes acquiring, by a requesting processor, lockbits associated with a memory structure of the shared memory storage system to be reserved for an overflowing transaction. The lockbits determine the granularity at which memory reservations for an overflow transaction are recorded. The method includes implementation of control mechanism for controlling concurrency between overflowing and non-overflowing transactions requested by processor devices in the multiprocessing system, the method enabling only one overflowing transaction to execute at a time in the multiprocessing system.

    摘要翻译： 一种用于处理事务性存储器系统中的溢出事务的系统，方法和计算机程序产品。 在具有一个或多个处理器设备和共享存储器存储系统的多处理系统中提供事务存储器系统，并且实现尽力而为的硬件事务存储器系统。 该方法包括由请求处理器获取与要为溢出事务保留的共享存储器存储系统的存储器结构相关联的锁定。 锁定确定记录溢出事务的存储器预留的粒度。 该方法包括实现用于控制多处理系统中的处理器设备所请求的溢出和非溢出事务之间的并发性的控制机制，该方法仅允许一个溢出事务在多处理系统中一次执行。