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    Local rollback for fault-tolerance in parallel computing systems
    4.
    发明授权
    Local rollback for fault-tolerance in parallel computing systems 有权
    并行计算系统容错的局部回滚

    公开(公告)号：US08103910B2

    公开(公告)日：2012-01-24

    申请号：US12696780

    申请日：2010-01-29

    申请人： Matthias A. Blumrich ,  Dong Chen ,  Alan Gara ,  Mark E. Giampapa ,  Philip Heidelberger ,  Martin Ohmacht ,  Burkhard Steinmacher-Burow ,  Krishnan Sugavanam

    发明人： Matthias A. Blumrich ,  Dong Chen ,  Alan Gara ,  Mark E. Giampapa ,  Philip Heidelberger ,  Martin Ohmacht ,  Burkhard Steinmacher-Burow ,  Krishnan Sugavanam

    IPC分类号： G06F11/00

    CPC分类号： G06F15/17381 ,  G06F9/30072

    摘要： A control logic device performs a local rollback in a parallel super computing system. The super computing system includes at least one cache memory device. The control logic device determines a local rollback interval. The control logic device runs at least one instruction in the local rollback interval. The control logic device evaluates whether an unrecoverable condition occurs while running the at least one instruction during the local rollback interval. The control logic device checks whether an error occurs during the local rollback. The control logic device restarts the local rollback interval if the error occurs and the unrecoverable condition does not occur during the local rollback interval.

    摘要翻译： 控制逻辑设备在并行超级计算系统中执行本地回滚。 超级计算系统包括至少一个高速缓冲存储器设备。 控制逻辑设备确定本地回滚间隔。 控制逻辑器件在本地回滚间隔中运行至少一条指令。 控制逻辑设备评估在本地回滚间隔期间运行至少一条指令时是否发生不可恢复的条件。 控制逻辑器件检查本地回滚期间是否发生错误。 如果发生错误，并且在本地回滚间隔期间不发生不可恢复的条件，则控制逻辑设备将重新启动本地回滚间隔。

    ATOMICITY: A MULTI-PRONGED APPROACH
    7.
    发明申请
    ATOMICITY: A MULTI-PRONGED APPROACH 审中-公开
    原理：多方面的方法

    公开(公告)号：US20110219215A1

    公开(公告)日：2011-09-08

    申请号：US13008546

    申请日：2011-01-18

    申请人： Matthias A. Blumrich ,  Dong Chen ,  Alan Gara ,  Philip Heidelberger ,  Martin Ohmarcht ,  Burkhard Steinmacher-Burow

    发明人： Matthias A. Blumrich ,  Dong Chen ,  Alan Gara ,  Philip Heidelberger ,  Martin Ohmarcht ,  Burkhard Steinmacher-Burow

    IPC分类号： G06F9/30

    CPC分类号： G06F9/524 ,  G06F12/08

    摘要： In a multiprocessor system with speculative execution, atomicity can be approached in several fashions. One approach is to have atomic instructions that achieve multiple functions and are guaranteed to complete. Another approach is to have blocks of code that are grouped to succeed or fail together. A system can incorporate more than one such approach. In implementing more than one approach, the system may prioritize one over another. When conflict detection is done through a directory lookup in cache memory, atomic instructions and atomicity related operations may be implemented in a cache data array access pipeline in that cache memory. This implementation may include feedback to the pipeline for implementing multiple functions within an atomic instruction and also for cascading atomic instructions.

    摘要翻译： 在具有推测性执行的多处理器系统中，可以以几种方式逼近原子性。 一种方法是具有实现多种功能并保证完成的原子指令。 另一种方法是将代码块分组成一起成功或失败。 系统可以包含多种这样的方法。 在实施多种方法时，系统可以优先考虑其他方法。 当通过高速缓冲存储器中的目录查找完成冲突检测时，原子指令和原子性相关操作可以在该高速缓冲存储器中的高速缓存数据阵列访问流水线中实现。 该实现可以包括用于在原子指令内实现多个功能并且还用于级联原子指令的流水线的反馈。

    LOW LATENCY MEMORY ACCESS AND SYNCHRONIZATION
    9.
    发明申请
    LOW LATENCY MEMORY ACCESS AND SYNCHRONIZATION 失效
    低延迟存储器访问和同步

    公开(公告)号：US20070204112A1

    公开(公告)日：2007-08-30

    申请号：US11617276

    申请日：2006-12-28

    申请人： Matthias Blumrich ,  Dong Chen ,  Paul Coteus ,  Alan Gara ,  Mark Giampapa ,  Philip Heidelberger ,  Dirk Hoenicke ,  Martin Ohmacht ,  Burkhard Steinmacher-Burow ,  Todd Takken ,  Pavlos Vranas

    发明人： Matthias Blumrich ,  Dong Chen ,  Paul Coteus ,  Alan Gara ,  Mark Giampapa ,  Philip Heidelberger ,  Dirk Hoenicke ,  Martin Ohmacht ,  Burkhard Steinmacher-Burow ,  Todd Takken ,  Pavlos Vranas

    IPC分类号： G06F12/14

    CPC分类号： G06F12/0862 ,  G06F9/52 ,  G06F2212/6028

    摘要： A low latency memory system access is provided in association with a weakly-ordered multiprocessor system. Each processor in the multiprocessor shares resources, and each shared resource has an associated lock within a locking device that provides support for synchronization between the multiple processors in the multiprocessor and the orderly sharing of the resources. A processor only has permission to access a resource when it owns the lock associated with that resource, and an attempt by a processor to own a lock requires only a single load operation, rather than a traditional atomic load followed by store, such that the processor only performs a read operation and the hardware locking device performs a subsequent write operation rather than the processor. A simple prefetching for non-contiguous data structures is also disclosed. A memory line is redefined so that in addition to the normal physical memory data, every line includes a pointer that is large enough to point to any other line in the memory, wherein the pointers to determine which memory line to prefetch rather than some other predictive algorithm. This enables hardware to effectively prefetch memory access patterns that are non-contiguous, but repetitive.

    摘要翻译： 与弱有序的多处理器系统相关联地提供低延迟存储器系统访问。 多处理器中的每个处理器共享资源，并且每个共享资源在锁定设备内具有关联的锁，其提供对多处理器中的多个处理器之间的同步的支持以及资源的有序共享。 当处理器拥有与该资源相关联的锁定时，处理器仅具有访问资源的权限，并且处理器拥有锁的尝试仅需要单个加载操作，而不是传统的原子负载后跟存储，使得处理器 只执行读取操作，并且硬件锁定装置执行后续的写入操作而不是处理器。 还公开了用于非连续数据结构的简单预取。 重新定义存储器线，使得除了正常的物理存储器数据之外，每行包括足够大的指针以指向存储器中的任何其他行，其中指针用于确定要预取的存储器行而不是一些其它预测 算法。 这使得硬件能够有效地预取不连续但重复的存储器访问模式。