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    Gate structure with low resistance for high power semiconductor devices
    1.
    发明授权
    Gate structure with low resistance for high power semiconductor devices 有权
    具有低电阻的门极结构，用于大功率半导体器件

    公开(公告)号：US07589377B2

    公开(公告)日：2009-09-15

    申请号：US11539482

    申请日：2006-10-06

    申请人： Mercedes P. Gomez ,  Emil M. Hanna ,  Wen-Ben Luo ,  Qingchun Zhang

    发明人： Mercedes P. Gomez ,  Emil M. Hanna ,  Wen-Ben Luo ,  Qingchun Zhang

    IPC分类号： H01L21/4763

    CPC分类号： H01L29/8083 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/42316 ,  H01L29/4925 ,  H01L29/66068 ,  H01L29/66734 ,  H01L29/66909

    摘要： In accordance with an embodiment of the present invention, a gate structure for a U-shape Metal-Oxide-Semiconductor (UMOS) device includes a dielectric layer formed into a U-shape having side walls and a floor to form a trench surrounding a dielectric layer interior region, a doped poly-silicon layer deposited adjacent to the dielectric layer within the dielectric layer interior region where the doped poly-silicon layer has side walls and a floor surrounding a doped poly-silicon layer interior region, a first metal layer deposited on the doped poly-silicon layer on a side opposite from the dielectric layer where the first metal layer has side walls and a floor surrounding a first metal layer interior region, and an undoped poly-silicon layer deposited to fill the first metal layer interior region.

    摘要翻译： 根据本发明的实施例，用于U形金属氧化物半导体（UMOS）器件的栅极结构包括形成为具有侧壁和底板的U形的电介质层，以形成围绕电介质的沟槽 在介电层内部区域中与电介质层相邻沉积的掺杂多晶硅层，其中掺杂多晶硅层具有侧壁和围绕掺杂多晶硅层内部区域的底板，沉积的第一金属层 在与第一金属层具有侧壁的电介质层相对的一侧上的掺杂多晶硅层和围绕第一金属层内部区域的地板和沉积以填充第一金属层内部区域的未掺杂多晶硅层 。

    Novel Gate Structure with Low Resistance for High Power Semiconductor Devices
    2.
    发明申请
    Novel Gate Structure with Low Resistance for High Power Semiconductor Devices 有权
    具有低电阻的大功率半导体器件的新型门结构

    公开(公告)号：US20080085591A1

    公开(公告)日：2008-04-10

    申请号：US11539482

    申请日：2006-10-06

    申请人： Mercedes P. Gomez ,  Emil M. Hanna ,  Wen-Ben Luo ,  Qingchun Zhang

    发明人： Mercedes P. Gomez ,  Emil M. Hanna ,  Wen-Ben Luo ,  Qingchun Zhang

    IPC分类号： H01L21/3205

    CPC分类号： H01L29/8083 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/42316 ,  H01L29/4925 ,  H01L29/66068 ,  H01L29/66734 ,  H01L29/66909

    摘要： In accordance with an embodiment of the present invention, a gate structure for a U-shape Metal-Oxide-Semiconductor (UMOS) device includes a dielectric layer formed into a U-shape having side walls and a floor to form a trench surrounding a dielectric layer interior region, a doped poly-silicon layer deposited adjacent to the dielectric layer within the dielectric layer interior region where the doped poly-silicon layer has side walls and a floor surrounding a doped poly-silicon layer interior region, a first metal layer deposited on the doped poly-silicon layer on a side opposite from the dielectric layer where the first metal layer has side walls and a floor surrounding a first metal layer interior region, and an undoped poly-silicon layer deposited to fill the first metal layer interior region.

    摘要翻译： 根据本发明的实施例，用于U形金属氧化物半导体（UMOS）器件的栅极结构包括形成为具有侧壁和底板的U形的电介质层，以形成围绕电介质的沟槽 在介电层内部区域中与电介质层相邻沉积的掺杂多晶硅层，其中掺杂多晶硅层具有侧壁和围绕掺杂多晶硅层内部区域的底板，沉积的第一金属层 在与第一金属层具有侧壁的电介质层相对的一侧上的掺杂多晶硅层和围绕第一金属层内部区域的地板和沉积以填充第一金属层内部区域的未掺杂多晶硅层 。