公开(公告)号：US20080085591A1

公开(公告)日：2008-04-10

申请号：US11539482

申请日：2006-10-06

申请人： Mercedes P. Gomez ,  Emil M. Hanna ,  Wen-Ben Luo ,  Qingchun Zhang

发明人： Mercedes P. Gomez ,  Emil M. Hanna ,  Wen-Ben Luo ,  Qingchun Zhang

IPC分类号： H01L21/3205

CPC分类号： H01L29/8083 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/42316 ,  H01L29/4925 ,  H01L29/66068 ,  H01L29/66734 ,  H01L29/66909

摘要： In accordance with an embodiment of the present invention, a gate structure for a U-shape Metal-Oxide-Semiconductor (UMOS) device includes a dielectric layer formed into a U-shape having side walls and a floor to form a trench surrounding a dielectric layer interior region, a doped poly-silicon layer deposited adjacent to the dielectric layer within the dielectric layer interior region where the doped poly-silicon layer has side walls and a floor surrounding a doped poly-silicon layer interior region, a first metal layer deposited on the doped poly-silicon layer on a side opposite from the dielectric layer where the first metal layer has side walls and a floor surrounding a first metal layer interior region, and an undoped poly-silicon layer deposited to fill the first metal layer interior region.

摘要翻译： 根据本发明的实施例，用于U形金属氧化物半导体（UMOS）器件的栅极结构包括形成为具有侧壁和底板的U形的电介质层，以形成围绕电介质的沟槽 在介电层内部区域中与电介质层相邻沉积的掺杂多晶硅层，其中掺杂多晶硅层具有侧壁和围绕掺杂多晶硅层内部区域的底板，沉积的第一金属层 在与第一金属层具有侧壁的电介质层相对的一侧上的掺杂多晶硅层和围绕第一金属层内部区域的地板和沉积以填充第一金属层内部区域的未掺杂多晶硅层 。

公开(公告)号：US07589377B2

公开(公告)日：2009-09-15

申请号：US11539482

申请日：2006-10-06

申请人： Mercedes P. Gomez ,  Emil M. Hanna ,  Wen-Ben Luo ,  Qingchun Zhang

发明人： Mercedes P. Gomez ,  Emil M. Hanna ,  Wen-Ben Luo ,  Qingchun Zhang

IPC分类号： H01L21/4763

CPC分类号： H01L29/8083 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/42316 ,  H01L29/4925 ,  H01L29/66068 ,  H01L29/66734 ,  H01L29/66909

摘要： In accordance with an embodiment of the present invention, a gate structure for a U-shape Metal-Oxide-Semiconductor (UMOS) device includes a dielectric layer formed into a U-shape having side walls and a floor to form a trench surrounding a dielectric layer interior region, a doped poly-silicon layer deposited adjacent to the dielectric layer within the dielectric layer interior region where the doped poly-silicon layer has side walls and a floor surrounding a doped poly-silicon layer interior region, a first metal layer deposited on the doped poly-silicon layer on a side opposite from the dielectric layer where the first metal layer has side walls and a floor surrounding a first metal layer interior region, and an undoped poly-silicon layer deposited to fill the first metal layer interior region.

摘要翻译： 根据本发明的实施例，用于U形金属氧化物半导体（UMOS）器件的栅极结构包括形成为具有侧壁和底板的U形的电介质层，以形成围绕电介质的沟槽 在介电层内部区域中与电介质层相邻沉积的掺杂多晶硅层，其中掺杂多晶硅层具有侧壁和围绕掺杂多晶硅层内部区域的底板，沉积的第一金属层 在与第一金属层具有侧壁的电介质层相对的一侧上的掺杂多晶硅层和围绕第一金属层内部区域的地板和沉积以填充第一金属层内部区域的未掺杂多晶硅层 。

公开(公告)号：US09640652B2

公开(公告)日：2017-05-02

申请号：US13608350

申请日：2012-09-10

申请人： Brett Adam Hull ,  Qingchun Zhang

发明人： Brett Adam Hull ,  Qingchun Zhang

IPC分类号： H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L29/16 ,  H01L29/45

CPC分类号： H01L29/0847 ,  H01L29/0623 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/7828

摘要： A semiconductor device may include a semiconductor layer having a first conductivity type, a well region of a second conductivity type in the semiconductor layer wherein the first and second conductivity types are different, and a terminal region of the first conductivity type in the well region. An epitaxial semiconductor layer may be on the surface of the semiconductor layer including the well region and the terminal region with the epitaxial semiconductor layer having the first conductivity type across the well and terminal regions. A gate electrode may be on the epitaxial semiconductor layer so that the epitaxial semiconductor layer is between the gate electrode and portions of the well region surrounding the terminal region at the surface of the semiconductor layer.

公开(公告)号：US09337268B2

公开(公告)日：2016-05-10

申请号：US13108366

申请日：2011-05-16

申请人： Qingchun Zhang ,  Craig Capell ,  Anant Agarwal ,  Sei-Hyung Ryu

发明人： Qingchun Zhang ,  Craig Capell ,  Anant Agarwal ,  Sei-Hyung Ryu

IPC分类号： H01L29/06 ,  H01L29/10 ,  H01L29/36 ,  H01L29/732 ,  H01L29/739 ,  H01L29/74 ,  H01L29/78 ,  H01L29/861 ,  H01L29/16

CPC分类号： H01L29/7813 ,  H01L21/0465 ,  H01L29/0615 ,  H01L29/0661 ,  H01L29/1004 ,  H01L29/1016 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/732 ,  H01L29/7397 ,  H01L29/74 ,  H01L29/861

摘要： A negative bevel edge termination for a Silicon Carbide (SiC) semiconductor device is disclosed. In one embodiment, the negative bevel edge termination includes multiple steps that approximate a smooth negative bevel edge termination at a desired slope. More specifically, in one embodiment, the negative bevel edge termination includes at least five steps, at least ten steps, or at least 15 steps. The desired slope is, in one embodiment, less than or equal to fifteen degrees. In one embodiment, the negative bevel edge termination results in a blocking voltage for the semiconductor device of at least 10 kilovolts (kV) or at least 12 kV. The semiconductor device is preferably, but not necessarily, a thyristor such as a power thyristor, a Bipolar Junction Transistor (BJT), an Insulated Gate Bipolar Transistor (IGBT), a U-channel Metal-Oxide-Semiconductor Field Effect Transistor (UMOSFET), or a PIN diode.

摘要翻译： 公开了一种用于碳化硅（SiC）半导体器件的负斜面边缘终端。 在一个实施例中，负斜边缘终端包括以期望的斜率近似平滑负斜面边缘终止的多个步骤。 更具体地，在一个实施例中，负斜边缘终止包括至少五个步骤，至少十个步骤或至少15个步骤。 在一个实施例中，期望的斜率小于或等于十五度。 在一个实施例中，负斜边缘终止导致半导体器件的阻挡电压为至少10千伏（kV）或至少12kV。 半导体器件优选但不一定是晶闸管，例如功率晶闸管，双极结晶体管（BJT），绝缘栅双极晶体管（IGBT），U沟道金属氧化物半导体场效应晶体管（UMOSFET） 或PIN二极管。

公开(公告)号：US08809904B2

公开(公告)日：2014-08-19

申请号：US12843113

申请日：2010-07-26

申请人： Qingchun Zhang ,  Anant Agarwal

发明人： Qingchun Zhang ,  Anant Agarwal

IPC分类号： H01L29/36

CPC分类号： H01L29/66378 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66234 ,  H01L29/66363 ,  H01L29/744

摘要： Electronic device structures including semiconductor ledge layers for surface passivation and methods of manufacturing the same are disclosed. In one embodiment, the electronic device includes a number of semiconductor layers of a desired semiconductor material having alternating doping types. The semiconductor layers include a base layer of a first doping type that includes a highly doped well forming a first contact region of the electronic device and one or more contact layers of a second doping type on the base layer that have been etched to form a second contact region of the electronic device. The etching of the one or more contact layers causes substantial crystalline damage, and thus interface charge, on the surface of the base layer. In order to passivate the surface of the base layer, a semiconductor ledge layer of the semiconductor material is epitaxially grown on at least the surface of the base layer.

摘要翻译： 公开了包括用于表面钝化的半导体凸缘层的电子器件结构及其制造方法。 在一个实施例中，电子器件包括具有交替掺杂类型的期望半导体材料的多个半导体层。 半导体层包括第一掺杂类型的基极层，其包括形成电子器件的第一接触区域的高度掺杂的阱和在基底层上的第二掺杂类型的一个或多个接触层，其被蚀刻以形成第二掺杂阱 电子设备的接触区域。 一个或多个接触层的蚀刻在基层的表面上引起显着的晶体损伤，并因此导致界面电荷。 为了钝化基底层的表面，半导体材料的半导体凸缘层至少在基底层的表面上外延生长。

公开(公告)号：US08637386B2

公开(公告)日：2014-01-28

申请号：US12719497

申请日：2010-03-08

申请人： Qingchun Zhang ,  Anant K. Agarwal ,  Tangali S. Sudarshan ,  Alexander Bolotnikov

发明人： Qingchun Zhang ,  Anant K. Agarwal ,  Tangali S. Sudarshan ,  Alexander Bolotnikov

IPC分类号： H01L21/22 ,  H01L21/38

CPC分类号： H01L29/1608 ,  H01L21/0465 ,  H01L21/223 ,  H01L29/0615 ,  H01L29/0657 ,  H01L29/0661 ,  H01L29/36 ,  H01L29/8613 ,  H01L29/872

摘要： An electronic device includes a silicon carbide layer having a first conductivity type and a main junction adjacent a surface of the silicon carbide layer, and a junction termination region at the surface of the silicon carbide layer adjacent the main junction. Charge in the junction termination region decreases with lateral distance from the main junction, and a maximum charge in the junction termination region may be less than about 2×1014 cm−2.

摘要翻译： 电子器件包括具有第一导电类型的碳化硅层和邻近碳化硅层的表面的主结，以及邻近主结的碳化硅层表面处的结终端区。 连接终端区域中的电荷随着与主结的横向距离而减小，并且接合终端区域中的最大电荷可能小于约2×1014cm-2。

公开(公告)号：US20130207123A1

公开(公告)日：2013-08-15

申请号：US13588329

申请日：2012-08-17

申请人： Jason Patrick Henning ,  Qingchun Zhang ,  Sei-Hyung Ryu ,  Anant Kumar Agarwal ,  John Williams Palmour ,  Scott Allen

发明人： Jason Patrick Henning ,  Qingchun Zhang ,  Sei-Hyung Ryu ,  Anant Kumar Agarwal ,  John Williams Palmour ,  Scott Allen

IPC分类号： H01L29/16 ,  H01L27/06

CPC分类号： H01L29/7805 ,  H01L21/046 ,  H01L21/049 ,  H01L25/18 ,  H01L27/0629 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/7806 ,  H01L2924/0002 ,  H01L2924/13091 ,  H02M7/003 ,  H02P7/04 ,  H01L2924/00

摘要： A power module is disclosed that includes a housing with an interior chamber wherein multiple switch modules are mounted within the interior chamber. The switch modules comprise multiple transistors and diodes that are interconnected to facilitate switching power to a load. In one embodiment, at least one of the switch modules supports a current density of at least 10 amperes per cm2.

摘要翻译： 公开了一种功率模块，其包括具有内部室的壳体，其中多个开关模块安装在内部室内。 开关模块包括多个晶体管和二极管，这些晶体管和二极管互连以便于将功率切换到负载。 在一个实施例中，至少一个开关模块支持每平方厘米至少10安培的电流密度。

公开(公告)号：US08460977B2

公开(公告)日：2013-06-11

申请号：US13338620

申请日：2011-12-28

申请人： Qingchun Zhang ,  Anant K. Agarwal

发明人： Qingchun Zhang ,  Anant K. Agarwal

IPC分类号： H01L21/335

CPC分类号： H01L29/7813 ,  H01L29/0615 ,  H01L29/0661 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/732 ,  H01L29/7397 ,  H01L29/744 ,  H01L29/7811 ,  H01L29/861 ,  H01L29/8613

摘要： A method of forming an electronic device, including forming a preliminary buffer layer on a drift layer, forming a first layer on the preliminary buffer layer, selectively etching the first layer to form a first mesa that exposes a portion of the preliminary buffer layer, and selectively etching the exposed portion of the preliminary buffer layer to form a second mesa that covers a first portion of the drift layer, that exposes a second portion of the drift layer, and that includes a mesa step that protrudes from the first mesa. Dopants are selectively implanted into the drift layer adjacent the second mesa to form a junction termination region in the drift layer. Dopants are selectively implanted through a horizontal surface of the mesa step into a portion of the drift layer beneath the mesa step to form a buried junction extension in the drift layer.

摘要翻译： 一种形成电子器件的方法，包括在漂移层上形成初步缓冲层，在预备缓冲层上形成第一层，选择性地蚀刻第一层以形成露出一部分初步缓冲层的第一台面;以及 选择性地蚀刻初步缓冲层的暴露部分以形成覆盖漂移层的第一部分的第二台面，其暴露漂移层的第二部分，并且包括从第一台面突出的台面台阶。 将掺杂剂选择性地注入到与第二台面相邻的漂移层中以在漂移层中形成结终止区域。 选择性地将掺杂剂通过台面台阶的水平表面植入台阶下面的漂移层的一部分，以在漂移层中形成掩埋结延伸。

公开(公告)号：US08330244B2

公开(公告)日：2012-12-11

申请号：US12492670

申请日：2009-06-26

申请人： Qingchun Zhang ,  Sei-Hyung Ryu ,  Anant Agarwal

发明人： Qingchun Zhang ,  Sei-Hyung Ryu ,  Anant Agarwal

IPC分类号： H01L27/095 ,  H01L29/47 ,  H01L29/812 ,  H01L31/07

CPC分类号： H01L29/0619 ,  H01L21/046 ,  H01L29/0615 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/872

摘要： A semiconductor device according to some embodiments includes a semiconductor layer having a first conductivity type and a surface in which an active region of the semiconductor device is defined. A plurality of spaced apart first doped regions are arranged within the active region. The plurality of first doped regions have a second conductivity type that is opposite the first conductivity type, have a first dopant concentration, and define a plurality of exposed portions of the semiconductor layer within the active region. The plurality of first doped regions are arranged as islands in the semiconductor layer. A second doped region in the semiconductor layer has the second conductivity type and has a second dopant concentration that is greater than the first dopant concentration.

摘要翻译： 根据一些实施例的半导体器件包括具有第一导电类型的半导体层和限定半导体器件的有源区的表面。 多个间隔开的第一掺杂区域被布置在有源区域内。 多个第一掺杂区域具有与第一导电类型相反的第二导电类型，具有第一掺杂剂浓度，并且在有源区内限定半导体层的多个暴露部分。 多个第一掺杂区域在半导体层中被布置为岛状。 半导体层中的第二掺杂区域具有第二导电类型并且具有大于第一掺杂剂浓度的第二掺杂剂浓度。

公开(公告)号：US20120273802A1

公开(公告)日：2012-11-01

申请号：US13547014

申请日：2012-07-11

申请人： Qingchun Zhang ,  Sei-Hyung Ryu

发明人： Qingchun Zhang ,  Sei-Hyung Ryu

IPC分类号： H01L29/24

CPC分类号： H01L29/872 ,  H01L29/0615 ,  H01L29/1608 ,  H01L29/47 ,  H01L29/861

摘要： An electronic device includes a silicon carbide drift region having a first conductivity type, a Schottky contact on the drift region, and a plurality of junction barrier Schottky (JBS) regions at a surface of the drift region adjacent the Schottky contact. The JBS regions have a second conductivity type opposite the first conductivity type and have a first spacing between adjacent ones of the JBS regions. The device further includes a plurality of surge protection subregions having the second conductivity type. Each of the surge protection subregions has a second spacing between adjacent ones of the surge protection subregions that is less than the first spacing.

摘要翻译： 电子器件包括具有第一导电类型的碳化硅漂移区，漂移区上的肖特基接触以及与肖特基接触相邻的漂移区的表面处的多个接合势垒肖特基（JBS）区。 JBS区域具有与第一导电类型相反的第二导电类型，并且在相邻的JBS区域之间具有第一间隔。 该装置还包括具有第二导电类型的多个浪涌保护子区域。 浪涌保护子区域中的每一个在相邻的浪涌保护子区域之间具有小于第一间隔的第二间隔。