公开(公告)号：US08000735B1

公开(公告)日：2011-08-16

申请号：US11001491

申请日：2004-12-01

申请人： Michael Barclay ,  Terry Lynn Cole ,  Richard Powell ,  William M. Johnson ,  David W. Smith ,  Ralf Findeisen ,  Derek Golightly

发明人： Michael Barclay ,  Terry Lynn Cole ,  Richard Powell ,  William M. Johnson ,  David W. Smith ,  Ralf Findeisen ,  Derek Golightly

IPC分类号： H04M1/00

CPC分类号： H04W88/02

摘要： A wireless communications device includes a host processing unit, a modem processing unit, and a memory transport interface. The wireless communications device typically runs a variety of software tasks, some of which require considerably more memory than others. By processing the memory intensive tasks with the host processing unit and assigning tasks requiring high computing power but relatively smaller memory to the modem processor unit, a smaller on-chip memory can be used for the modem processor unit tasks. In addition, by using a messaging transport interface to transfer data between tasks running on different processing units, smaller local memories can be used in place of a shared memory. For example, by allocating and storing L1 tasks at the modem processing unit and allocating/storing L2 and L3 tasks at the host processing unit, duplicate memory components may be reduced or removed, thereby lowering system costs and improving system efficiency.

摘要翻译： 无线通信设备包括主机处理单元，调制解调器处理单元和存储器传输接口。 无线通信设备通常运行各种软件任务，其中一些需要比其他任务更多的存储器。 通过使用主机处理单元处理存储器密集型任务并且为调制解调器处理器单元分配需要高计算能力但是相对较小的存储器的任务，可以使用较小的片上存储器用于调制解调器处理器单元任务。 此外，通过使用消息传送接口在不同处理单元之间运行的任务之间传送数据，可以使用较小的本地存储器代替共享存储器。 例如，通过在调制解调器处理单元分配和存储L1任务并在主处理单元分配/存储L2和L3任务，可以减少或移除重复的存储器组件，从而降低系统成本并提高系统效率。

公开(公告)号：US07492747B2

公开(公告)日：2009-02-17

申请号：US11316499

申请日：2005-12-21

申请人： Axel Wachtler ,  Richard Powell ,  Michael Grell ,  Ralf Findeisen

发明人： Axel Wachtler ,  Richard Powell ,  Michael Grell ,  Ralf Findeisen

IPC分类号： H04L9/32

CPC分类号： H04L9/3271 ,  H04L9/3247 ,  H04L2209/80 ,  H04W8/245 ,  H04W12/10 ,  H04W12/12 ,  H04W84/04 ,  H04W88/02

摘要： The present invention relates methods for patching WWAN (Wireless Wide Area Network) communication devices and corresponding WWAN communication devices, integrated circuit chips and computer-readable media. The WWAN communication device includes a first processor, a second processor and a memory. The first processor is arranged to process patches updating software running on the WWAN communication device. The second processor is arranged to provide a first set of the patches to the first processor. The memory stores a second set of the patches to be processed by the first processor. The second processor is further arranged to send a patch end signal to the first processor, the patch end signal causing the first processor to stop processing of patches provided by the second processor. The first processor is further arranged to process the patches stored in the memory independently of the patch end signal.

摘要翻译： 本发明涉及用于修补WWAN（无线广域网）通信设备和相应的WWAN通信设备，集成电路芯片和计算机可读介质的方法。 WWAN通信设备包括第一处理器，第二处理器和存储器。 第一处理器被设置为处理在WWAN通信设备上运行的更新软件的补丁。 第二处理器被布置成向第一处理器提供第一组补丁。 存储器存储要由第一处理器处理的第二组补丁。 第二处理器还被布置为向第一处理器发送补丁结束信号，补丁结束信号使得第一处理器停止对由第二处理器提供的补丁的处理。 第一处理器还被布置成独立于补丁结束信号来处理存储在存储器中的补丁。

公开(公告)号：US20070028296A1

公开(公告)日：2007-02-01

申请号：US11316499

申请日：2005-12-21

申请人： Axel Wachtler ,  Richard Powell ,  Michael Grell ,  Ralf Findeisen

发明人： Axel Wachtler ,  Richard Powell ,  Michael Grell ,  Ralf Findeisen

IPC分类号： H04L9/32

CPC分类号： H04L9/3271 ,  H04L9/3247 ,  H04L2209/80 ,  H04W8/245 ,  H04W12/10 ,  H04W12/12 ,  H04W84/04 ,  H04W88/02

摘要： The present invention relates methods for patching WWAN (Wireless Wide Area Network) communication devices and corresponding WWAN communication devices, integrated circuit chips and computer-readable media. The WWAN communication device includes a first processor, a second processor and a memory. The first processor is arranged to process patches updating software running on the WWAN communication device. The second processor is arranged to provide a first set of the patches to the first processor. The memory stores a second set of the patches to be processed by the first processor. The second processor is further arranged to send a patch end signal to the first processor, the patch end signal causing the first processor to stop processing of patches provided by the second processor. The first processor is further arranged to process the patches stored in the memory independently of the patch end signal.

摘要翻译： 本发明涉及用于修补WWAN（无线广域网）通信设备和相应的WWAN通信设备，集成电路芯片和计算机可读介质的方法。 WWAN通信设备包括第一处理器，第二处理器和存储器。 第一处理器被设置为处理在WWAN通信设备上运行的更新软件的补丁。 第二处理器被布置成向第一处理器提供第一组补丁。 存储器存储要由第一处理器处理的第二组补丁。 第二处理器还被布置为向第一处理器发送补丁结束信号，补丁结束信号使得第一处理器停止对由第二处理器提供的补丁的处理。 第一处理器还被布置成独立于补丁结束信号来处理存储在存储器中的补丁。

公开(公告)号：US08612729B2

公开(公告)日：2013-12-17

申请号：US11957930

申请日：2007-12-17

申请人： Garth D. Hillman ,  Geoffrey Strongin ,  Andrew R. Rawson ,  Gary H. Simpson ,  Ralf Findeisen

发明人： Garth D. Hillman ,  Geoffrey Strongin ,  Andrew R. Rawson ,  Gary H. Simpson ,  Ralf Findeisen

IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F11/30 ,  G06F12/14

CPC分类号： G06F9/30145 ,  G06F9/30174 ,  G06F9/30178 ,  G06F9/30181 ,  G06F9/328 ,  G06F9/3885 ,  G06F21/572 ,  G06F21/76

摘要： In one embodiment, a processor comprises a programmable map and a circuit. The programmable map is configured to store data that identifies at least one instruction for which an architectural modification of an instruction set architecture implemented by the processor has been defined, wherein the processor does not implement the modification. The circuitry is configured to detect the instruction or its memory operands and cause a transition to Known Good Code (KGC), wherein the KGC is protected from unauthorized modification and is provided from an authenticated entity. The KGC comprises code that, when executed, emulates the modification. In another embodiment, an integrated circuit comprises at least one processor core; at least one other circuit; and a KGC source configured to supply KGC to the processor core for execution. The KGC comprises interface code for the other circuit whereby an application executing on the processor core interfaces to the other circuit through the KGC.

公开(公告)号：US20090276617A1

公开(公告)日：2009-11-05

申请号：US12355900

申请日：2009-01-19

申请人： Michael Grell ,  Ralf Findeisen ,  Frank Schuecke

发明人： Michael Grell ,  Ralf Findeisen ,  Frank Schuecke

IPC分类号： G06F9/00 ,  G06F12/00 ,  G06F1/24 ,  G06F9/44

CPC分类号： G06F21/575

摘要： A CPU, a computer system and a secure boot mechanism are provided in which a symmetric encryption key may be incorporated into a non-volatile memory area of the CPU core, thereby substantially avoiding any tampering of the encryption key by external sources. Moreover, pre-boot information may be internally stored in the CPU and may be retrieved upon a reset or power-on event in order to verify a signed boot information on the basis of the internal symmetric encryption key. Furthermore, the BIOS information may be efficiently updated by generating a signature using the internal encryption key.

摘要翻译： 提供了CPU，计算机系统和安全引导机制，其中对称加密密钥可以被并入CPU核心的非易失性存储器区域中，从而基本上避免了外部源对加密密钥的任何篡改。 此外，预引导信息可以内部存储在CPU中，并且可以在复位或开机事件时检索，以便基于内部对称加密密钥来验证签名的引导信息。 此外，可以通过使用内部加密密钥生成签名来有效地更新BIOS信息。

公开(公告)号：US20090193230A1

公开(公告)日：2009-07-30

申请号：US12022446

申请日：2008-01-30

申请人： Ralf Findeisen ,  Geoffrey S. Strongin ,  Andrew R. Rawson ,  Garth D. Hillman ,  Gary H. Simpson

发明人： Ralf Findeisen ,  Geoffrey S. Strongin ,  Andrew R. Rawson ,  Garth D. Hillman ,  Gary H. Simpson

IPC分类号： G06F15/80

CPC分类号： G06F21/74 ,  G06F21/445 ,  G06F21/575 ,  G06F21/71 ,  G06F2221/2101 ,  G06F2221/2105

摘要： A computer system includes a main processor and a security control processor that is coupled to the main processor and configured to control and monitor an operational state of the main processor. To ensure the computer system may be trusted, the security control processor may be configured to hold the main processor in a slave mode during initialization of the security control processor such that the main processor is not operable to fetch and execute instructions from an instruction source external to the main processor, for example. In addition, the security control processor may be configured to initialize the operational state of the main processor to a predetermined state by transferring to the main processor via a control interface one or more instructions and to cause the main processor to execute the one or more instructions while the main processor is held in the slave mode.

摘要翻译： 计算机系统包括主处理器和安全控制处理器，其连接到主处理器并且被配置为控制和监视主处理器的操作状态。 为了确保计算机系统可以被信任，安全控制处理器可以被配置为在安全控制处理器的初始化期间将主处理器保持在从模式，使得主处理器不可操作地从指令源外部获取和执行指令 以主处理器为例。 此外，安全控制处理器可以被配置为通过经由控制接口将一个或多个指令传送到主处理器来将主处理器的操作状态初始化到预定状态，并且使主处理器执行一个或多个指令 而主处理器则保持在从模式。

公开(公告)号：US07831813B2

公开(公告)日：2010-11-09

申请号：US11957848

申请日：2007-12-17

申请人： Garth D. Hillman ,  Geoffrey Strongin ,  Andrew R. Rawson ,  Gary H. Simpson ,  Ralf Findeisen

发明人： Garth D. Hillman ,  Geoffrey Strongin ,  Andrew R. Rawson ,  Gary H. Simpson ,  Ralf Findeisen

IPC分类号： G06F9/455

CPC分类号： G06F9/30174 ,  G06F9/30178 ,  G06F9/30181 ,  G06F21/57

摘要： In one embodiment, a processor comprises a programmable map and a circuit. The programmable map is configured to store data that identifies at least one instruction for which an architectural modification of an instruction set architecture implemented by the processor has been defined, wherein the processor does not implement the modification. The circuitry is configured to detect the instruction or its memory operands and cause a transition to Known Good Code (KGC), wherein the KGC is protected from unauthorized modification and is provided from an authenticated entity. The KGC comprises code that, when executed, emulates the modification. In another embodiment, an integrated circuit comprises at least one processor core; at least one other circuit; and a KGC source configured to supply KGC to the processor core for execution. The KGC comprises interface code for the other circuit whereby an application executing on the processor core interfaces to the other circuit through the KGC.

摘要翻译： 在一个实施例中，处理器包括可编程映射和电路。 可编程映射被配置为存储标识至少一个指令的数据，对于该指令已经定义了由处理器实现的指令集架构的架构修改，其中处理器不实现修改。 电路被配置为检测指令或其存储器操作数并且导致转换到已知的良好代码（KGC），其中KGC被保护免受未经授权的修改，并且从认证实体提供。 KGC包括在执行时模拟修改的代码。 在另一实施例中，集成电路包括至少一个处理器核心; 至少一个其他电路; 以及配置为向处理器核心提供KGC以供执行的KGC源。 KGC包括用于另一电路的接口代码，由此在处理器核上执行的应用程序通过KGC与另一电路接口。

公开(公告)号：US20090158015A1

公开(公告)日：2009-06-18

申请号：US11957848

申请日：2007-12-17

申请人： Garth D. Hillman ,  Geoffrey Strongin ,  Andrew R. Rawson ,  Gary H. Simpson ,  Ralf Findeisen

发明人： Garth D. Hillman ,  Geoffrey Strongin ,  Andrew R. Rawson ,  Gary H. Simpson ,  Ralf Findeisen

IPC分类号： G06F9/30

CPC分类号： G06F9/30174 ,  G06F9/30178 ,  G06F9/30181 ,  G06F21/57

摘要： In one embodiment, a processor comprises a programmable map and a circuit. The programmable map is configured to store data that identifies at least one instruction for which an architectural modification of an instruction set architecture implemented by the processor has been defined, wherein the processor does not implement the modification. The circuitry is configured to detect the instruction or its memory operands and cause a transition to Known Good Code (KGC), wherein the KGC is protected from unauthorized modification and is provided from an authenticated entity. The KGC comprises code that, when executed, emulates the modification. In another embodiment, an integrated circuit comprises at least one processor core; at least one other circuit; and a KGC source configured to supply KGC to the processor core for execution. The KGC comprises interface code for the other circuit whereby an application executing on the processor core interfaces to the other circuit through the KGC.

摘要翻译： 在一个实施例中，处理器包括可编程映射和电路。 可编程映射被配置为存储标识至少一个指令的数据，对于该指令已经定义了由处理器实现的指令集架构的架构修改，其中处理器不实现修改。 电路被配置为检测指令或其存储器操作数并且导致转换到已知的良好代码（KGC），其中KGC被保护免受未经授权的修改，并且从认证实体提供。 KGC包括在执行时模拟修改的代码。 在另一实施例中，集成电路包括至少一个处理器核心; 至少一个其他电路; 以及配置为向处理器核心提供KGC以供执行的KGC源。 KGC包括用于另一电路的接口代码，由此在处理器核上执行的应用程序通过KGC与另一电路接口。

公开(公告)号：US20100174890A1

公开(公告)日：2010-07-08

申请号：US11957930

申请日：2007-12-17

申请人： Garth D. Hillman ,  Geoffrey Strongin ,  Andrew R. Rawson ,  Gary H. Simpson ,  Ralf Findeisen

发明人： Garth D. Hillman ,  Geoffrey Strongin ,  Andrew R. Rawson ,  Gary H. Simpson ,  Ralf Findeisen

IPC分类号： G06F9/30 ,  G06F9/44

CPC分类号： G06F9/30145 ,  G06F9/30174 ,  G06F9/30178 ,  G06F9/30181 ,  G06F9/328 ,  G06F9/3885 ,  G06F21/572 ,  G06F21/76

摘要： In one embodiment, a processor comprises a programmable map and a circuit. The programmable map is configured to store data that identifies at least one instruction for which an architectural modification of an instruction set architecture implemented by the processor has been defined, wherein the processor does not implement the modification. The circuitry is configured to detect the instruction or its memory operands and cause a transition to Known Good Code (KGC), wherein the KGC is protected from unauthorized modification and is provided from an authenticated entity. The KGC comprises code that, when executed, emulates the modification. In another embodiment, an integrated circuit comprises at least one processor core; at least one other circuit; and a KGC source configured to supply KGC to the processor core for execution. The KGC comprises interface code for the other circuit whereby an application executing on the processor core interfaces to the other circuit through the KGC.

摘要翻译： 在一个实施例中，处理器包括可编程映射和电路。 可编程映射被配置为存储标识至少一个指令的数据，对于该指令已经定义了由处理器实现的指令集架构的架构修改，其中处理器不实现修改。 电路被配置为检测指令或其存储器操作数并且导致转换到已知的良好代码（KGC），其中KGC被保护免受未经授权的修改，并且从认证实体提供。 KGC包括在执行时模拟修改的代码。 在另一实施例中，集成电路包括至少一个处理器核心; 至少一个其他电路; 以及配置为向处理器核心提供KGC以供执行的KGC源。 KGC包括用于另一电路的接口代码，由此在处理器核上执行的应用程序通过KGC与另一电路接口。

公开(公告)号：US07672828B2

公开(公告)日：2010-03-02

申请号：US11315977

申请日：2005-12-21

申请人： Michael Fiedler ,  Ralf Findeisen ,  Michael Grell ,  Matthias Lenk

发明人： Michael Fiedler ,  Ralf Findeisen ,  Michael Grell ,  Matthias Lenk

IPC分类号： G06F9/44

CPC分类号： G06F9/455 ,  G06F8/20

摘要： A software development technique is provided using target system virtualization software simulating behaviour of a target system. A target device driver running on a host system issues memory access commands to the target system virtualization software rather than to a memory interface unit of the host system. The memory interface unit may be an SRAM (Static Random Access Memory) interface. The target system may be an EGPRS (Enhanced General Packet Radio Service) modem.

摘要翻译： 使用目标系统虚拟化软件模拟目标系统的行为来提供软件开发技术。 在主机系统上运行的目标设备驱动程序向目标系统虚拟化软件而不是主机系统的存储器接口单元发出内存访问命令。 存储器接口单元可以是SRAM（静态随机存取存储器）接口。 目标系统可以是EGPRS（增强型通用分组无线业务）调制解调器。