公开(公告)号：US20050138584A1

公开(公告)日：2005-06-23

申请号：US10738708

申请日：2003-12-17

申请人： Michael Beattie ,  Anirudh Devgan ,  Byron Krauter ,  Hui Zheng

发明人： Michael Beattie ,  Anirudh Devgan ,  Byron Krauter ,  Hui Zheng

IPC分类号： G06F9/45 ,  G06F17/50

CPC分类号： G06F17/5036 ,  G06F2217/40

摘要： A method, system, and product are disclosed for determining a voltage drop across an entire integrated circuit package. A geometric description of the entire integrated circuit package is determined. The description is subdivided into non-uniform areas. A resistance of each one of the non-uniform areas is determined. A resistive netlist of the entire integrated circuit package is then determined by combining the resistance of each one of the non-uniform areas. The package is then simulated utilizing the netlist to determine the voltage drop across the entire integrated circuit package.

摘要翻译： 公开了一种用于确定跨整个集成电路封装的电压降的方法，系统和产品。 确定整个集成电路封装的几何描述。 描述细分为非均匀区域。 确定每个不均匀区域的电阻。 然后通过组合每个非均匀区域的电阻来确定整个集成电路封装的电阻网表。 然后使用网表模拟封装以确定整个集成电路封装的电压降。

公开(公告)号：US20070300191A1

公开(公告)日：2007-12-27

申请号：US11849346

申请日：2007-09-03

申请人： Michael Beattie ,  Anirudh Devgan ,  Byron Krauter ,  Hui Zheng

发明人： Michael Beattie ,  Anirudh Devgan ,  Byron Krauter ,  Hui Zheng

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A method of modeling electromagnetism in an irregular conductive plane, by dividing the surface into a grid of unequal and unaligned rectangles, assigning a circuit node location to a center of each rectangle, and calculating capacitive and inductive parameters based on the center circuit node locations. Rectangulation is accomplished using automated, recursive bisection. Capacitive segments are assigned to each circuit node and coincide with the corresponding rectangles. Inductive segments are assigned between adjacent rectangle pairs, with a width of an inductive segment defined as the common boundary of the corresponding pair of rectangles and the length of the inductive segment defined as the normal distance between circuit nodes of the two rectangles. Placement of the circuit nodes at the centers of the rectangles significantly reduces the number of nodes and segments, and provides a faster yet comprehensive analysis framework.

摘要翻译： 通过将表面划分成不等长且不对齐的矩形的网格，将电路节点位置分配给每个矩形的中心，以及基于中心电路节点位置计算电容和电感参数，来对不规则导电平面中的电磁体进行建模的方法。 使用自动递归二分法实现矩形化。 电容段被分配给每个电路节点并与相应的矩形重合。 感应片段被分配在相邻的矩形对之间，其中感应片段的宽度被定义为相应的一对矩形的公共边界，并且感应片段的长度被定义为两个矩形的电路节点之间的正常距离。 电路节点在矩形中心的放置显着减少了节点和节点的数量，并提供了一个更快而又全面的分析框架。

公开(公告)号：US20060282798A1

公开(公告)日：2006-12-14

申请号：US11152580

申请日：2005-06-14

申请人： Michael Beattie ,  Anirudh Devgan ,  Byron Krauter ,  Hui Zheng

发明人： Michael Beattie ,  Anirudh Devgan ,  Byron Krauter ,  Hui Zheng

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A method of modeling electromagnetism in an irregular conductive plane, by dividing the surface into a grid of unequal and unaligned rectangles, assigning a circuit node location to a center of each rectangle, and calculating capacitive and inductive parameters based on the center circuit node locations. Rectangulation is accomplished using automated, recursive bisection. Capacitive segments are assigned to each circuit node and coincide with the corresponding rectangles. Inductive segments are assigned between adjacent rectangle pairs, with a width of an inductive segment defined as the common boundary of the corresponding pair of rectangles and the length of the inductive segment defined as the normal distance between circuit nodes of the two rectangles. Placement of the circuit nodes at the centers of the rectangles significantly reduces the number of nodes and segments, and provides a faster yet comprehensive analysis framework.

摘要翻译： 通过将表面划分成不等长且不对齐的矩形的网格，将电路节点位置分配给每个矩形的中心，以及基于中心电路节点位置计算电容和电感参数，来对不规则导电平面中的电磁体进行建模的方法。 使用自动递归二分法实现矩形化。 电容段被分配给每个电路节点并与相应的矩形重合。 感应片段被分配在相邻的矩形对之间，其中感应片段的宽度被定义为相应的一对矩形的公共边界，并且感应片段的长度被定义为两个矩形的电路节点之间的正常距离。 电路节点在矩形中心的放置显着减少了节点和节点的数量，并提供了一个更快而又全面的分析框架。

公开(公告)号：US20070136044A1

公开(公告)日：2007-06-14

申请号：US11301731

申请日：2005-12-13

申请人： Michael Beattie ,  Byron Krauter ,  Hui Zheng

发明人： Michael Beattie ,  Byron Krauter ,  Hui Zheng

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A method of simulating a circuit parameter such as voltage or current for a dominantly linear circuit by constructing a circuit equation matrix whose elements correspond to nodes of the circuit, decoupling linear and nonlinear contributions to the circuit parameter based on a partition of an inverse matrix of the circuit equation matrix, computing linear and nonlinear components using the decoupled contributions, and combining the nonlinear and linear components to yield a state of the circuit parameter for a given time step. The computation of the nonlinear component includes Newton-Raphson iterations to linearize nonlinear devices of the circuit, wherein the Newton-Raphson technique is applied to the right-hand side of the circuit state matrix equation. The computations are iteratively repeated for successive time steps which are advantageously separated by a constant time interval to avoid further recalculation of the state matrix.

摘要翻译： 一种通过构造电路方程矩阵来模拟电路参数如电压或电流的方法，该电路方程矩阵的元素对应于电路的节点，基于电路参数的线性和非线性贡献，将基线 电路方程矩阵，使用解耦贡献计算线性和非线性分量，以及组合非线性和线性分量以产生给定时间步长的电路参数的状态。 非线性分量的计算包括用于线性化电路的非线性器件的Newton-Raphson迭代，其中将Newton-Raphson技术应用于电路状态矩阵方程的右侧。 对于连续的时间步长迭代重复计算，这些时间步长有利地以恒定的时间间隔隔开，以避免进一步重新计算状态矩阵。

公开(公告)号：US20080072189A1

公开(公告)日：2008-03-20

申请号：US11942270

申请日：2007-11-19

申请人： Michael Bowen ,  Alina Deutsch ,  Gerard Kopcsay ,  Byron Krauter ,  Barry Rubin ,  Howard Smith ,  David Widiger

发明人： Michael Bowen ,  Alina Deutsch ,  Gerard Kopcsay ,  Byron Krauter ,  Barry Rubin ,  Howard Smith ,  David Widiger

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： An integrated circuit chip has new Frequency dependent RLC extraction and modeling providing on chip integrity and noise verification and the extraction and modeling employs: A) 2D scan line algorithm for the collection of adjacent signal and power conductor coordinates; B) In core pair-wise frequency Dependent RL extraction; C) In core equivalent circuit synthesis; D) caching and partitioning RL extraction techniques for run time efficiency; and E) Techniques for synthesizing stable circuits to represent frequency dependent RL circuits for non-mono tonic R12.

摘要翻译： 集成电路芯片具有新的频率相关RLC提取和建模，提供片上完整性和噪声验证，提取和建模采用：A）用于收集相邻信号和电源导线坐标的2D扫描线算法; B）在核心配对频率从属RL提取中; C）在核心等效电路合成中; D）缓存和分区RL提取技术，用于运行时效率; 和E）用于合成稳定电路以表示用于非单音增益R 12的频率相关RL电路的技术。

公开(公告)号：US20050218908A1

公开(公告)日：2005-10-06

申请号：US10818578

申请日：2004-04-06

申请人： Alina Deutsch ,  Gerard Kopcsay ,  Byron Krauter ,  Barry Rubin ,  Howard Smith

发明人： Alina Deutsch ,  Gerard Kopcsay ,  Byron Krauter ,  Barry Rubin ,  Howard Smith

IPC分类号： G01R21/00 ,  G01R29/26 ,  G01R31/317 ,  G05B24/02 ,  G05F1/00 ,  G06F17/50 ,  H01L23/522 ,  H01L23/528 ,  H02J1/00 ,  H02J3/12 ,  H02J3/18

CPC分类号： G01R31/31721 ,  H01L23/5225 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： The present invention relates to a method for analyzing the noise prediction within one or more electrical circuits, wherein the electrical circuits have a power mesh grid distribution system that feeds power levels to the electrical circuits that are connected by signal wires. After identifying a driver and receiver electrical circuit to be analyzed, a power block is generated that is associated with the driver and receiver electrical circuit by partitioning an area of a power mesh grid distribution system into a power block that can be modeled with lossy transmission line techniques. Next, signal wires situated between the driver and receiver electrical circuits are partitioned into signal blocks that can be modeled with lossy transmission line techniques. Lastly, the power blocks and signal blocks associated with the electrical circuits are analyzed in order to predict the noise performance within the electrical circuits.

摘要翻译： 本发明涉及一种用于分析一个或多个电路内的噪声预测的方法，其中电路具有功率网格分布系统，其将功率电平馈送到通过信号线连接的电路。 在识别要分析的驱动器和接收器电路之后，通过将功率网格分布系统的区域划分成可以用有损传输线建模的功率块来产生与驱动器和接收器电路相关联的功率块 技术 接下来，位于驱动器和接收器电路之间的信号线被分割成可以用有损传输线技术建模的信号块。 最后，分析与电路相关联的功率块和信号块，以便预测电路内的噪声性能。

公开(公告)号：US20080111604A1

公开(公告)日：2008-05-15

申请号：US12014501

申请日：2008-01-15

申请人： David Boerstler ,  Eskinder Hailu ,  Byron Krauter ,  Kazuhiko Miki ,  Jieming Qi

发明人： David Boerstler ,  Eskinder Hailu ,  Byron Krauter ,  Kazuhiko Miki ,  Jieming Qi

IPC分类号： H03K3/017

CPC分类号： G06F1/10 ,  H03K5/1565

摘要： A method, an apparatus, and a computer program are provided to measure and/or correct duty cycles. Duty cycles of various signals, specifically clocking signals, are important. However, measurement of very high frequency signals, off-chip, and in a laboratory environment can be very difficult and present numerous problems. To combat problems associated with making off-chip measurements and adjustments of signal duty cycles, comparisons are made between input signals and divided input signals that allow for easy measurement and adjustment of on-chip signals, including clocking signals.

摘要翻译： 提供了一种方法，装置和计算机程序来测量和/或校正占空比。 各种信号的占空比，特别是时钟信号是很重要的。 然而，测量非常高频率的信号，芯片外和实验室环境可能是非常困难的并且存在许多问题。 为了解决与片外测量和信号占空比调整相关的问题，可以比较输入信号和分频输入信号，从而便于测量和调整片上信号，包括时钟信号。

公开(公告)号：US20060212739A1

公开(公告)日：2006-09-21

申请号：US11082973

申请日：2005-03-17

申请人： David Boerstler ,  Eskinder Hailu ,  Byron Krauter ,  Kazuhiko Miki ,  Jieming Qi

发明人： David Boerstler ,  Eskinder Hailu ,  Byron Krauter ,  Kazuhiko Miki ,  Jieming Qi

IPC分类号： G06F1/04

CPC分类号： G06F1/10 ,  H03K5/1565

摘要： A method, an apparatus, and a computer program are provided to measure and/or correct duty cycles. Duty cycles of various signals, specifically clocking signals, are important. However, measurement of very high frequency signals, off-chip, and in a laboratory environment can be very difficult and present numerous problems. To combat problems associated with making off-chip measurements and adjustments of signal duty cycles, comparisons are made between input signals and divided input signals that allow for easy measurement and adjustment of on-chip signals, including clocking signals.

摘要翻译： 提供了一种方法，装置和计算机程序来测量和/或校正占空比。 各种信号的占空比，特别是时钟信号是很重要的。 然而，测量非常高频率的信号，芯片外和实验室环境可能是非常困难的并且存在许多问题。 为了解决与片外测量和信号占空比调整相关的问题，可以比较输入信号和分频输入信号，从而便于测量和调整片上信号，包括时钟信号。

公开(公告)号：US20060190881A1

公开(公告)日：2006-08-24

申请号：US11048422

申请日：2005-02-01

申请人： Haihua Su ,  David Widiger ,  Ying Liu ,  Byron Krauter ,  Chandramouli Kashyap

发明人： Haihua Su ,  David Widiger ,  Ying Liu ,  Byron Krauter ,  Chandramouli Kashyap

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A system and method for estimating propagation noise that is induced by a non-zero noise glitch at the input of the driver circuit. Such propagation noise is a function of both the input noise glitch and the driver output effective capacitive load, which is typically part of the total wiring capacitance due to resistive shielding in deep sub-micron interconnects. The noise-driven effective capacitance solution provided herein also estimates the propagation noise induced by a non-zero noise glitch at the input of the driving gate. Gate propagation noise rules describing a relationship between the output noise properties and the input noise properties and the output loading capacitance are used within the noise-driven effective capacitance process to determine the linear Thevenin model of the driving gate. The linearized Thevenin driver model is then employed to analyze both the propagation noise and the combined coupling and propagation noise typically seen in global signal nets.

摘要翻译： 用于估计在驱动器电路的输入处由非零噪声毛刺引起的传播噪声的系统和方法。 这种传播噪声是输入噪声毛刺和驱动器输出有效电容性负载两者的函数，这通常是由于深亚微米互连中的电阻屏蔽而导致的总布线电容的一部分。 本文提供的噪声驱动的有效电容解决方案还估计在驱动门的输入处由非零噪声毛刺引起的传播噪声。 在噪声驱动的有效电容过程中使用描述输出噪声特性和输入噪声特性与输出负载电容之间的关系的门传播噪声规则来确定驱动门的线性戴维宁模型。 然后使用线性化的戴维南驱动器模型来分析传播噪声和通常在全局信号网中看到的组合耦合和传播噪声。