公开(公告)号：US07146520B2

公开(公告)日：2006-12-05

申请号：US10436210

申请日：2003-05-12

申请人： Michael Billeci ,  Timothy G. McNamara ,  Ching-Lung L. Tong ,  David Webber

发明人： Michael Billeci ,  Timothy G. McNamara ,  Ching-Lung L. Tong ,  David Webber

IPC分类号： G06F1/04 ,  G06F1/14

CPC分类号： G06F1/04

摘要： A method and apparatus for operating a clock in a processor having asymmetrically mirrored base-mirror units is disclosed. The method includes initializing a base-unit and a mirror-unit of the processor to the same state, and starting the mirror-unit-clock one clock cycle later than the base-unit-clock.

摘要翻译： 公开了一种用于在具有不对称镜像的基镜单元的处理器中操作时钟的方法和装置。 该方法包括将处理器的基本单元和镜像单元初始化为相同的状态，并且比基本单位时钟晚一个时钟周期启动镜像单元时钟。

公开(公告)号：US07568138B2

公开(公告)日：2009-07-28

申请号：US11459942

申请日：2006-07-26

申请人： Adolf Martens ,  Walter Niklaus ,  Dietmar Schmunkamp ,  Scott Barnett Swaney ,  Ching-Lung L. Tong ,  Tobias Webel

发明人： Adolf Martens ,  Walter Niklaus ,  Dietmar Schmunkamp ,  Scott Barnett Swaney ,  Ching-Lung L. Tong ,  Tobias Webel

IPC分类号： G01R31/28

CPC分类号： G06F11/2236 ,  G01R31/318569

摘要： A computer implemented method and data processing system are provided for preventing firmware defects from disrupting logic clocks. In response to a firmware interface requesting a scan operation for a functional unit, protection logic allows a scan enable to activate to the functional unit only if the logic clocks are stopped to that functional unit, otherwise the scan enable is not activated, an error is indicated, and an interrupt is presented to firmware. Also, in response to a command from a firmware interface to stop the logic clocks to a functional unit, protection logic allows the clocks to be stopped to the functional unit only if the functional unit is already indicating a catastrophic error, otherwise the clocks are not stopped, an error is indicated, and an interrupt is presented to firmware.

摘要翻译： 提供了一种计算机实现的方法和数据处理系统，用于防止固件缺陷中断逻辑时钟。 响应于对功能单元请求扫描操作的固件接口，只有当逻辑时钟停止到该功能单元时，保护逻辑允许扫描使能才能激活到功能单元，否则扫描使能不被激活，错误是 指示，并向固件呈现中断。 另外，响应于来自固件界面的命令将逻辑时钟停止到功能单元，保护逻辑允许时钟停止到功能单元，只有当功能单元已经指示灾难性错误时，否则时钟不是 停止，指示错误，并向固件提供中断。

公开(公告)号：US20080028266A1

公开(公告)日：2008-01-31

申请号：US11459942

申请日：2006-07-26

申请人： Adolf Martens ,  Walter Niklaus ,  Dietmar Schmunkamp ,  Scott Barnett Swaney ,  Ching-Lung L. Tong ,  Tobias Webel

发明人： Adolf Martens ,  Walter Niklaus ,  Dietmar Schmunkamp ,  Scott Barnett Swaney ,  Ching-Lung L. Tong ,  Tobias Webel

IPC分类号： G01R31/28

CPC分类号： G06F11/2236 ,  G01R31/318569

摘要： A computer implemented method and data processing system are provided for preventing firmware defects from disrupting logic clocks. In response to a firmware interface requesting a scan operation for a functional unit, protection logic allows a scan enable to activate to the functional unit only if the logic clocks are stopped to that functional unit, otherwise the scan enable is not activated, an error is indicated, and an interrupt is presented to firmware. Also, in response to a command from a firmware interface to stop the logic clocks to a functional unit, protection logic allows the clocks to be stopped to the functional unit only if the functional unit is already indicating a catastrophic error, otherwise the clocks are not stopped, an error is indicated, and an interrupt is presented to firmware.

摘要翻译： 提供了一种计算机实现的方法和数据处理系统，用于防止固件缺陷中断逻辑时钟。 响应于对功能单元请求扫描操作的固件接口，只有当逻辑时钟停止到该功能单元时，保护逻辑允许扫描使能才能激活到功能单元，否则扫描使能不被激活，错误是 指示，并向固件呈现中断。 另外，响应于来自固件界面的命令将逻辑时钟停止到功能单元，保护逻辑允许时钟停止到功能单元，只有当功能单元已经指示灾难性错误时，否则时钟不是 停止，指示错误，并向固件呈现中断。

公开(公告)号：US06333680B1

公开(公告)日：2001-12-25

申请号：US09677348

申请日：2000-10-02

申请人： Howard H. Smith ,  Alina Deutsch ,  Ching-Lung L. Tong ,  Rolf H. Nijhuis

发明人： Howard H. Smith ,  Alina Deutsch ,  Ching-Lung L. Tong ,  Rolf H. Nijhuis

IPC分类号： H03B524

CPC分类号： G01R27/2605 ,  G01R31/04

摘要： An exemplary embodiment of the invention is a method of characterizing capacitances of a plurality of integrated circuit interconnects. The method includes coupling a first oscillator to a first integrated circuit interconnect and coupling a second oscillator to a second integrated circuit interconnect. The first oscillator is activated to characterize the sum of (i) coupling capacitance between the first integrated-circuit interconnect and the second integrated-circuit interconnect and (ii) ground capacitance between the first integrated-circuit interconnect and a ground. In addition, both of the first oscillator and the second oscillator are activated to characterize the ground capacitance between the first integrated-circuit interconnect and the ground.

摘要翻译： 本发明的示例性实施例是表征多个集成电路互连的电容的方法。 该方法包括将第一振荡器耦合到第一集成电路互连并将第二振荡器耦合到第二集成电路互连。 激活第一振荡器以表征（i）第一集成电路互连和第二集成电路互连之间的耦合电容和（ii）第一集成电路互连和地之间的接地电容之和的和。 此外，第一振荡器和第二振荡器都被激活以表征第一集成电路互连和地之间的接地电容。