Envelope packet architecture for broadband engine
    1.
    发明申请
    Envelope packet architecture for broadband engine 有权
    宽带引擎的信封包架构

    公开(公告)号:US20060059273A1

    公开(公告)日:2006-03-16

    申请号:US10942422

    申请日:2004-09-16

    IPC分类号: G06F15/16

    CPC分类号: H04L1/188

    摘要: The present invention provides for sending an envelope and replying to an envelope. A transmitter is configured to send an envelope. A receiver is coupled to the transmitter, wherein the receiver is configured to receive the envelope and generate a reply envelope. A send buffer is coupled to the transmitter. A receive buffer is coupled to the receiver. A retry timer is coupled to the transmitter, wherein the retry timer is configured to reset upon the receipt of a reply envelope correlated to the transmit envelope. The transmitter is configured to retransmit an envelope if the transmitter does not receive a corresponding reply envelope within a selected time period as determined by the retry timer. This leads to a decrease in the total number of envelopes, transmitted from both the transmitter and the receiver.

    摘要翻译: 本发明提供发送信封并回复信封。 发射机被配置为发送信封。 接收机耦合到发射机,其中接收机被配置为接收信封并产生回复信封。 发送缓冲器耦合到发送器。 接收缓冲器耦合到接收器。 重试定时器耦合到发射机,其中重试定时器被配置为在接收到与发射包络相关的应答包络时复位。 如果发射机在由重试定时器确定的选定时间段内没有接收到对应的应答包络,则发射机被配置为重发信封。 这导致从发射机和接收机两者发送的信封总数的减少。

    Methods and apparatus for reducing command reissue latency
    2.
    发明申请
    Methods and apparatus for reducing command reissue latency 审中-公开
    减少命令重发延迟的方法和装置

    公开(公告)号:US20070174556A1

    公开(公告)日:2007-07-26

    申请号:US11340751

    申请日:2006-01-26

    IPC分类号: G06F13/00

    CPC分类号: G06F12/0831

    摘要: In a first aspect, a first method of reducing reissue latency of a command received in a command processing pipeline from one of a plurality of units coupled to a bus is provided. The first method includes the steps of (1) from a first unit coupled to the bus, receiving a first command on the bus requiring access to a cacheline; (2) determining a state of the cacheline required by the first command by accessing cacheline state information stored in each of the plurality of units; (3) determining whether a second command received on the bus requires access to the cacheline before the state of the cacheline is returned to the first unit; and (4) if so, storing the second command in a buffer. Numerous other aspects are provided.

    摘要翻译: 在第一方面,提供了一种减少在命令处理流水线中从耦合到总线的多个单元之一接收的命令的重发等待时间的第一方法。 第一种方法包括以下步骤:(1)从耦合到总线的第一单元接收需要访问高速缓存线的总线上的第一命令; (2)通过访问存储在所述多个单元中的每个单元中的高速缓存行状态信息来确定所述第一命令所需的高速缓存行的状态; (3)在高速缓存行的状态返回到第一单元之前,确定在总线上接收的第二命令是否需要访问高速缓存线; 和(4)如果是,则将第二命令存储在缓冲器中。 提供了许多其他方面。

    Method and apparatus for implementing enhanced vertical ECC storage in a dynamic random access memory
    3.
    发明申请
    Method and apparatus for implementing enhanced vertical ECC storage in a dynamic random access memory 失效
    用于在动态随机存取存储器中实现增强的垂直ECC存储的方法和装置

    公开(公告)号:US20060200723A1

    公开(公告)日:2006-09-07

    申请号:US11071086

    申请日:2005-03-03

    IPC分类号: H03M13/00

    CPC分类号: G06F11/1044

    摘要: A method and apparatus are provided for implementing enhanced vertical ECC storage in a dynamic random access memory. A dynamic random access memory (DRAM) is split into a plurality of groups. Each group resides inside a DRAM row address strobe (RAS) page so that multiple locations inside a group can be accessed without incurring an additional RAS access penalty. Each group is logically split into a plurality of segments for storing data with at least one segment for storing ECC for the data segments. For a write operation, data are written in a data segment and then ECC for the data are written in an ECC segment. For a read operation, ECC are read from an ECC segment, then data are read from the data segment.

    摘要翻译: 提供了一种用于在动态随机存取存储器中实现增强的垂直ECC存储的方法和装置。 动态随机存取存储器(DRAM)被分成多个组。 每个组都驻留在DRAM行地址选通(RAS)页面中,从而可以访问组内的多个位置,而不会引起额外的RAS访问损失。 每个组在逻辑上分成多个段,用于存储具有用于存储数据段的ECC的至少一个段的数据。 对于写入操作,将数据写入数据段,然后将ECC用于数据写入ECC段。 对于读取操作,从ECC段读取ECC,然后从数据段读取数据。

    Buffer management for a target channel adapter
    4.
    发明申请
    Buffer management for a target channel adapter 失效
    目标通道适配器的缓冲区管理

    公开(公告)号:US20050083956A1

    公开(公告)日:2005-04-21

    申请号:US10688220

    申请日:2003-10-16

    IPC分类号: H04L12/56 H04L12/54

    摘要: A method, apparatus, system, and signal-bearing medium that in an embodiment determine whether a current number of buffers allocated to a queue pair is less than a maximum number of buffers for the queue pair, decide whether a current number of buffers allocated to an operation type is less than a maximum number of buffers for the operation, and allocate a buffer to the queue pair if the queue pair requests the buffer for an operation having the operation type and the determining and the deciding are true. In this way, too much buffer space is prevented from being assigned to particular operation and to a particular queue pair.

    摘要翻译: 一种方法,装置,系统和信号承载介质,其在一个实施例中确定分配给队列对的当前数量的缓冲器是否小于队列对的最大缓冲器数量,决定当前分配给 操作类型小于操作缓冲区的最大数量,如果队列对请求具有操作类型的操作的缓冲区以及确定和判定为真,则将缓冲区分配给队列对。 以这种方式,防止将太多的缓冲区空间分配给特定的操作和特定的队列对。