公开(公告)号：US07590965B1

公开(公告)日：2009-09-15

申请号：US11642179

申请日：2006-12-19

申请人： Michael George Ingoldby ,  James E. Ogden ,  Jeffrey C. Ward ,  Stacey Secatch ,  Restu I. Ismail ,  Thomas E. Fischaber

发明人： Michael George Ingoldby ,  James E. Ogden ,  Jeffrey C. Ward ,  Stacey Secatch ,  Restu I. Ismail ,  Thomas E. Fischaber

IPC分类号： G06F17/50

CPC分类号： G06F17/5054

摘要： Methods of generating a PLD design implementation according to a design architecture tailored to specified requirements. A hardware description language (HDL) description for the PLD design includes at least one parameter value for the PLD design that will affect the preferred implementation of the design. This parameter value is passed to a high-level language (HLL) function, which is used to determine a tailored design architecture in accordance with the specified needs of the target application. The HLL function returns data specifying the tailored design architecture. This data is used in generating an implementation of the PLD design that follows the constraints imposed by the tailored design architecture. The result can be, for example, a logic gate representation of the PLD design, a netlist of the design, or a bitstream implementing the design in a target PLD.

摘要翻译： 根据针对特定要求定制的设计架构生成PLD设计实现的方法。 PLD设计的硬件描述语言（HDL）描述包括将影响设计的首选实现的PLD设计的至少一个参数值。 该参数值被传递给高级语言（HLL）函数，用于根据目标应用程序的指定需求来确定定制的设计架构。 HLL函数返回指定定制设计架构的数据。 该数据用于生成遵循定制设计架构强加的约束的PLD设计的实现。 结果可以是例如PLD设计的逻辑门表示，设计的网表，或者在目标PLD中实现设计的比特流。

公开(公告)号：US07506298B1

公开(公告)日：2009-03-17

申请号：US11642173

申请日：2006-12-19

申请人： Michael George Ingoldby ,  James E. Ogden ,  Stacey Secatch

发明人： Michael George Ingoldby ,  James E. Ogden ,  Stacey Secatch

IPC分类号： G06F17/50

CPC分类号： G06F17/5054

摘要： Computer-implemented methods of mapping a logical representation of a memory to physical memory, e.g., in a programmable logic device (PLD). The logical representation of the memory is input into the computer, which generates an initial solution (e.g., a column-based solution) for the memory. In a column-based solution, the primitives are arranged such that each column includes only one type of primitive. The column-based solution generated in this step uses the minimum number of primitives attainable by a column-based approach. The column-based solution is then modified to reduce multiplexing, e.g., by replacing two primitives that are cascaded in depth with two primitives that are cascaded in width. In some embodiments, the total number of primitives can be reduced by the modification. The resulting physical representation of the memory is then output, and can be utilized, if desired, to create an implementation of the memory targeted to a PLD.

摘要翻译： 计算机实现的将存储器的逻辑表示映射到物理存储器的方法，例如在可编程逻辑器件（PLD）中。 存储器的逻辑表示被输入到计算机中，其为存储器生成初始解决方案（例如，基于列的解决方案）。 在基于列的解决方案中，原语被布置为使得每列仅包括一种类型的原语。 在此步骤中生成的基于列的解决方案使用基于列的方法可获得的最小数量的图元。 然后对基于列的解决方案进行修改以减少多路复用，例如，通过将两个深度级联的基元替换为以宽度级联的两个图元。 在一些实施例中，可以通过修改来减少原始图案的总数。 然后输出所产生的存储器的物理表示，并且如果需要，可以利用这些物理表示来创建针对PLD的存储器的实现。

公开(公告)号：US07057546B1

公开(公告)日：2006-06-06

申请号：US10871072

申请日：2004-06-18

申请人： Stacey Secatch ,  James E. Ogden

发明人： Stacey Secatch ,  James E. Ogden

IPC分类号： H03M1/36

CPC分类号： G06F7/74

摘要： Apparatuses for binary priority encoding are described. A binary priority encoder (100, 100L) includes a data input bus (139), a first logic tree (110) coupled to receive data from the input bus (139), and a second logic tree (130) coupled to receive a portion of the data from the input bus (139). The first logic tree (110) is configured to provide a flag signal (154) indicating whether at least one bit of the data is active. The first logic tree (110) is configured to provide control signals. The second logic tree (130) is coupled to receive the control signals. The second logic tree (130) is configured to select first partial addresses from the portion of the data responsive to the control signals. The control signals are further provided to the second logic tree (130) as second partial addresses.

摘要翻译： 描述二进制优先级编码的装置。 二进制优先级编码器（100,100L）包括数据输入总线（139），耦合以从输入总线（139）接收数据的第一逻辑树（110）和耦合以接收数据的第二逻辑树 来自输入总线（139）的部分数据。 第一逻辑树（110）被配置为提供指示数据的至少一位是否是活动的标志信号（154）。 第一逻辑树（110）被配置为提供控制信号。 第二逻辑树（130）被耦合以接收控制信号。 第二逻辑树（130）被配置为响应于控制信号从数据的该部分中选择第一部分地址。 控制信号作为第二部分地址进一步提供给第二逻辑树（130）。

公开(公告)号：US07433980B1

公开(公告)日：2008-10-07

申请号：US11111434

申请日：2005-04-21

申请人： Scott J. Fischaber ,  James E. Ogden

发明人： Scott J. Fischaber ,  James E. Ogden

IPC分类号： G06F9/315

CPC分类号： G11C7/1006

摘要： Circuits and methods of rearranging the order of data in a memory having asymmetric input and output ports are disclosed. According to one embodiment, a method comprises steps of providing an input port of a memory having an input width and output port having an output width which is different than the input width. A plurality of data words are received at the input of the memory, wherein each data word has a width corresponding to the input width. The order of the plurality of input data words is rearranged; and an output word based upon the rearranged data words and having a width corresponding to the output width is generated. Various circuits and algorithms for implementing the methods are also disclosed.

摘要翻译： 公开了在具有不对称输入和输出端口的存储器中重新排列数据顺序的电路和方法。 根据一个实施例，一种方法包括以下步骤：提供具有输入宽度和输出端口的存储器的输入端口，其输出宽度不同于输入宽度。 在存储器的输入处接收多个数据字，其中每个数据字具有对应于输入宽度的宽度。 多个输入数据字的顺序被重新排列; 并且产生基于重新排列的数据字并具有与输出宽度相对应的宽度的输出字。 还公开了用于实现该方法的各种电路和算法。

公开(公告)号：US5533103A

公开(公告)日：1996-07-02

申请号：US473941

申请日：1995-06-07

申请人： Stephen D. Peavey ,  James E. Ogden ,  William J. Hoyt ,  Ino Dunn ,  Paul E. Zmuda ,  David A. Jamroga ,  Jacob W. Jorgensen

发明人： Stephen D. Peavey ,  James E. Ogden ,  William J. Hoyt ,  Ino Dunn ,  Paul E. Zmuda ,  David A. Jamroga ,  Jacob W. Jorgensen

IPC分类号： H04M3/42 ,  H04M3/51 ,  H04M11/10

CPC分类号： H04M3/51 ,  H04M3/5158 ,  H04M3/42221 ,  Y10S379/904

摘要： An automated computer calling system is disclosed for correlating diverse types of recorded information, such as voice or video, with data records that have been previously stored and/or simultaneously entered. The calling system is capable of simultaneously recording and processing multiple customer transactions, and verifying the transactions on the basis of the recorded information. In a preferred embodiment, the calling system includes: a customer database; one or more agent stations connected to a communications network; a call processor for controlling the communication between the agent stations and the customers and for selectively recording at least a portion of the conversation between a customer and an agent; a call manager for monitoring the customer communications and enabling data exchange between the customer database and the agent station, and for supplying the call processor with information required to initiate and terminate the communication; and a call recorder for linking the recorded voice information with the corresponding customer data record.

摘要翻译： 公开了一种自动计算机呼叫系统，用于将各种类型的记录信息（例如语音或视频）与先前存储和/或同时输入的数据记录相关联。 呼叫系统能够同时记录和处理多个客户交易，并且基于记录的信息来验证交易。 在优选实施例中，呼叫系统包括：客户数据库; 连接到通信网络的一个或多个代理站; 呼叫处理器，用于控制代理站和客户之间的通信，并且用于选择性地记录客户和代理之间的谈话的至少一部分; 用于监视客户通信并启用客户数据库和代理站之间的数据交换的呼叫管理器，以及向呼叫处理器提供启动和终止通信所需的信息; 以及用于将记录的语音信息与相应的客户数据记录相关联的呼叫记录器。

公开(公告)号：US07539789B1

公开(公告)日：2009-05-26

申请号：US11503889

申请日：2006-08-14

申请人： James E. Ogden

发明人： James E. Ogden

IPC分类号： G06F3/00 ,  G06F13/00

CPC分类号： G06F5/065 ,  G06F5/14

摘要： Memory circuits that concatenate multiple FIFOs in parallel to increase the overall depth of the memory circuits. Asymmetric input and output ports can be provided by including a deserializer on the write interface of the memory circuit and/or a serializer on the read interface of the memory circuit. The deserializer disperses the data evenly across all FIFOs, minimizing the write-to-read latency. In some embodiments, at most two of the FIFOs are active at any given time, one being written and one being read, which reduces the overall power consumption of the memory circuit compared to known structures.

摘要翻译： 并行连接多个FIFO的存储器电路，以增加存储器电路的总体深度。 可以通过在存储器电路的写接口上包括解串器和/或在存储器电路的读接口上的串行器来提供非对称输入和输出端口。 解串器将数据均匀分散在所有FIFO中，从而最小化写入 - 读取延迟。 在一些实施例中，至少两个FIFO在任何给定时间是有效的，一个被写入，一个被读取，与已知的结构相比降低了存储器电路的总功耗。