公开(公告)号：US06762611B2

公开(公告)日：2004-07-13

申请号：US10010504

申请日：2001-12-05

申请人： Michael Hübner ,  Gunnar Krause ,  Justus Kuhn ,  Jochen Müller ,  Peter Pöchmüller ,  Jürgen Weidenhöfer

发明人： Michael Hübner ,  Gunnar Krause ,  Justus Kuhn ,  Jochen Müller ,  Peter Pöchmüller ,  Jürgen Weidenhöfer

IPC分类号： G01R1073

CPC分类号： G01R31/319 ,  G01R31/318505 ,  G01R31/318511 ,  G01R31/31905 ,  G11C29/006 ,  G11C29/48

摘要： A test configuration for testing a plurality of integrated circuits, in particular fast semiconductor memory modules located on a wafer, in parallel. The test configuration includes a carrier board for bringing up electrical signal lines belonging to a test system, contact-making needles for producing electrical connections with contact areas on the circuits to be tested, and a plurality of active modules that are arranged on the carrier board. The active modules are each assigned to one of the circuits to be tested in parallel, and are each case inserted into the signal path between the test system and the associated circuit to be tested. In a preferred embodiment, the active modules are arranged at least partly overlapping, based on a direction at right angles to the plane of the carrier board.

摘要翻译： 用于同时测试位于晶片上的多个集成电路，特别是快速半导体存储器模块的测试配置。 测试配置包括用于提升属于测试系统的电信号线的承载板，用于产生与要测试的电路上的接触区域的电连接的接触针，以及布置在承载板上的多个有源模块 。 有源模块分别被分配给要并联测试的电路之一，并且每一个都被插入测试系统和要测试的相关电路之间的信号路径中。 在优选实施例中，有源模块基于与载板的平面成直角的方向至少部分地重叠布置。

公开(公告)号：US06853206B2

公开(公告)日：2005-02-08

申请号：US10736356

申请日：2003-12-15

申请人： Michael Hübner ,  Gunnar Krause ,  Justus Kuhn ,  Jochen Müller ,  Peter P{hacek over (o)}chmüller ,  Jürgen Weidenhöfer

发明人： Michael Hübner ,  Gunnar Krause ,  Justus Kuhn ,  Jochen Müller ,  Peter P{hacek over (o)}chmüller ,  Jürgen Weidenhöfer

IPC分类号： G01R31/3185 ,  G01R31/319 ,  G11C29/00 ,  G11C29/48 ,  G01R31/02 ,  G01R31/28

CPC分类号： G01R31/319 ,  G01R31/318505 ,  G01R31/318511 ,  G01R31/31905 ,  G11C29/006 ,  G11C29/48

摘要： A test configuration for testing a plurality of integrated circuits, in particular fast semiconductor memory modules located on a wafer, in parallel. The test configuration includes a carrier board for bringing up electrical signal lines belonging to a test system, contact-making needles for producing electrical connections with contact areas on the circuits to be tested, and a plurality of active modules that are arranged on the carrier board. The active modules are each assigned to one of the circuits to be tested in parallel, and are each case inserted into the signal path between the test system and the associated circuit to be tested. In a preferred embodiment, the active modules are arranged at least partly overlapping, based on a direction at right angles to the plane of the carrier board.

摘要翻译： 用于同时测试位于晶片上的多个集成电路，特别是快速半导体存储器模块的测试配置。 测试配置包括用于提升属于测试系统的电信号线的承载板，用于产生与要测试的电路上的接触区域的电连接的接触针，以及布置在承载板上的多个有源模块 。 有源模块分别被分配给要并联测试的电路之一，并且每一个都被插入测试系统和要测试的相关电路之间的信号路径中。 在优选实施例中，有源模块基于与载板的平面成直角的方向至少部分地重叠布置。