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1.发明申请Spectral and information theoretic method of test point, partial-scan, and full-scan flip-flop insertion to improve integrated circuit testability 有权测试点，部分扫描和全扫描触发器插入的光谱和信息理论方法，以提高集成电路可测试性公开(公告)号：US20100102825A1
公开(公告)日：2010-04-29
申请号：US12454476
申请日：2009-05-18
CPC分类号： G01R31/318583 , G06F17/505 , G06F2217/14 , Y10T29/49204
摘要： Design for testability (DFT) algorithms, which use both gradient descent and linear programming (LP) algorithms to insert test points (TPs) and/or scanned flip-flops (SFFs) into large circuits to make them testable are described. Scanning of either all flip-flops or a subset of flip-flops is supported. The algorithms measure testability using probabilities computed from logic simulation, Shannon's entropy measure (from information theory), and spectral analysis of the circuit in the frequency domain. The DFT hardware inserter methods uses toggling rates of the flip-flops (analyzed using digital signal processing (DSP) methods) and Shannon entropy measures of flip-flops to select flip-flops for scan. The optimal insertion of the DFT hardware reduces the amount of DFT hardware, since the gradient descent and linear program optimizations trade off inserting a TP versus inserting an SFF. The linear programs find the optimal solution to the optimization, and the entropy measures are used to maximize information flow through the circuit-under-test (CUT). The methods limit the amount of additional circuit hardware for test points and scan flip-flops.
摘要翻译： 描述了使用梯度下降和线性规划（LP）算法将测试点（TP）和/或扫描的触发器（SFF）插入大电路以使其可测试的可测性（DFT）算法的设计。 支持所有触发器或触发器子集的扫描。 该算法使用从逻辑仿真，香农熵测量（信息理论）和频域中的电路的频谱分析计算出的概率来测量可测性。 DFT硬件插入器方法使用触发器的转换速率（使用数字信号处理（DSP）方法分析））和触发器的Shannon熵测量来选择用于扫描的触发器。 DFT硬件的最佳插入减少了DFT硬件的数量，因为梯度下降和线性程序优化使插入TP与插入SFF成为交换。 线性程序找到优化的最优解，并且使用熵测量来最大化通过电路下测试（CUT）的信息流。 该方法限制了测试点和扫描触发器的附加电路硬件的数量。
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2.发明授权Spectral and information theoretic method of test point, partial-scan, and full-scan flip-flop insertion to improve integrated circuit testability 有权测试点，部分扫描和全扫描触发器插入的光谱和信息理论方法，以提高集成电路可测试性公开(公告)号：US08164345B2
公开(公告)日：2012-04-24
申请号：US12454476
申请日：2009-05-18
CPC分类号： G01R31/318583 , G06F17/505 , G06F2217/14 , Y10T29/49204
摘要： Design for testability (DFT) algorithms, which use both gradient descent and linear programming (LP) algorithms to insert test points (TPs) and/or scanned flip-flops (SFFs) into large circuits to make them testable are described. Scanning of either all flip-flops or a subset of flip-flops is supported. The algorithms measure testability using probabilities computed from logic simulation, Shannon's entropy measure (from information theory), and spectral analysis of the circuit in the frequency domain. The DFT hardware inserter methods uses toggling rates of the flip-flops (analyzed using digital signal processing (DSP) methods) and Shannon entropy measures of flip-flops to select flip-flops for scan. The optimal insertion of the DFT hardware reduces the amount of DFT hardware, since the gradient descent and linear program optimizations trade off inserting a TP versus inserting an SFF. The linear programs find the optimal solution to the optimization, and the entropy measures are used to maximize information flow through the circuit-under-test (CUT). The methods limit the amount of additional circuit hardware for test points and scan flip-flops.
摘要翻译： 描述了使用梯度下降和线性规划（LP）算法将测试点（TP）和/或扫描的触发器（SFF）插入大电路以使其可测试的可测性（DFT）算法的设计。 支持所有触发器或触发器子集的扫描。 该算法使用从逻辑仿真，香农熵测量（信息理论）和频域中的电路的频谱分析计算出的概率来测量可测性。 DFT硬件插入器方法使用触发器的转换速率（使用数字信号处理（DSP）方法分析））和触发器的Shannon熵测量来选择用于扫描的触发器。 DFT硬件的最佳插入减少了DFT硬件的数量，因为梯度下降和线性程序优化使插入TP与插入SFF成为交换。 线性程序找到优化的最优解，并且使用熵测量来最大化通过电路下测试（CUT）的信息流。 该方法限制了测试点和扫描触发器的附加电路硬件的数量。
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公开(公告)号：US5831437A
公开(公告)日：1998-11-03
申请号：US582365
申请日：1996-01-05
IPC分类号： G01R31/316 , G01R31/3167 , G01R31/317 , G01R31/3183 , G01R31/02
CPC分类号： G01R31/318342 , G01R31/316 , G01R31/3167 , G01R31/318307 , G01R31/317
摘要： The present invention relates to a method and apparatus for generating test patterns to test an analog or mixed signal circuit. A signal flow graph of the analog circuit is determined. The signal flow graph is inverted and reverse simulated with good and bad outputs to determine component tolerances of the circuit given circuit output tolerances. The inverted signal flow graph is backtraced from analog outputs to obtain analog input sinusoids which justify the analog outputs.
摘要翻译： 本发明涉及一种用于产生测试模式以测试模拟或混合信号电路的方法和装置。 确定模拟电路的信号流程图。 信号流图被反转并用良好和不良输出反向模拟，以确定给定电路输出公差的电路的元件公差。 反相信号流图从模拟输出回溯，以获得模拟输入正弦曲线，以证明模拟输出。
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4.发明授权公开(公告)号：US06308300B1
公开(公告)日：2001-10-23
申请号：US09326516
申请日：1999-06-04
IPC分类号： G06F1750
CPC分类号： G01R31/316 , G01R31/3167
摘要： The present invention relates to a method and apparatus for testing analog and mixed analog and digital circuits in which test waveforms are generated for testing the analog circuit. The analog circuit can be represented by a directed circuit graph. The directed circuit graph represents nodes of components of the circuit under test connected by directed edges for components having inputs or outputs which effect other components and undirected edges for components in the circuit that are bidirectional. For example, undirected edges are assigned to bidirectional elements such as resistors and capacitors and directed edges are assigned to transistors. The directed graph is partitioned into partitions that carry a signal from the primary inputs toward the primary outputs in the circuit under test. Feedback and local feedback are captured in a single partition. The partition of a faulty component is determined and the operating point of the partition is established to activate the fault. The fault effects on the transfer function of each partition are determined by fault sensitization and fault effect propagation.
摘要翻译： 本发明涉及一种用于测试模拟和混合模拟和数字电路的方法和装置，其中产生用于测试模拟电路的测试波形。 模拟电路可以由有向电路图表示。 定向电路图表示通过有向边缘连接的被测电路的部件的节点，该部件具有输入或输出，其对于双向的电路中的部件的其它部件和无向边缘起作用。 例如，无向边被分配给诸如电阻器和电容器的双向元件，并且将有向边缘分配给晶体管。 有向图被划分为在主要输入端向被测电路中的主输出端传送信号的分区。 反馈和本地反馈在单个分区中捕获。 确定故障部件的分区，并建立分区的工作点以激活故障。 每个分区的传递函数的故障影响由故障敏感和故障效应传播决定。
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5.发明授权Method and apparatus for combined stuck-at fault and partial-scanned delay-fault built-in self test 失效组合故障和部分扫描延迟故障内置自检的方法和装置公开(公告)号：US06247154B1
公开(公告)日：2001-06-12
申请号：US09260836
申请日：1999-03-02
IPC分类号： H04B1700
CPC分类号： G01R31/318586
摘要： This invention relates to a method and apparatus for combined stuck-fault testing and partial scan delay-fault built-in self testing (BIST). For partial scan delay-fault BIST, the circuit is modeled for breaking all flip-flop feedback cycles in the circuit. A selection of flip-flops to be scanned to break all sequential cycles is determined from an optimal feedback vertex set. A digest, devour and tidy-up (DDT) heuristic can be used on a weighted signed graph formed from an S-graph of the circuit to determine an optimal feedback vertex set. Determined partial scan delay fault BIST hazards can be removed from the circuit by inserting parity flippers to invert selected paths during testing. The same DDT heuristic can be used to determine optimal placement of the parity flippers in the circuit.
摘要翻译： 本发明涉及一种用于组合卡死故障测试和部分扫描延迟故障内置自检（BIST）的方法和装置。 对于部分扫描延迟故障BIST，该电路建模用于断开电路中的所有触发器反馈周期。 从最佳反馈顶点集确定要扫描以破坏所有连续周期的触发器的选择。 摘要，吞噬和整理（DDT）启发式可用于由电路的S图形成的加权有符号图，以确定最佳反馈顶点集。 确定的部分扫描延迟故障BIST危险可以通过插入奇偶校验脚蹼在测试期间反转所选路径从电路中移除。 可以使用相同的滴滴涕启发式来确定电路中奇偶校验脚蹼的最佳位置。
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公开(公告)号：US06812724B2
公开(公告)日：2004-11-02
申请号：US10372448
申请日：2003-02-24
申请人： Lan Rao , Michael L. Bushnell
发明人： Lan Rao , Michael L. Bushnell
IPC分类号： G01R3102
CPC分类号： G01R31/3008
摘要： The present invention relates to a method and system for detecting defects within an integrated circuit in which one or more parameters of a classifier are determined by graphical evaluation of IDDQ current measurements. Parameters of the classifier can include a number of bands for a good integrated circuit, a width of a band for a good chip, a width ratio between any two bands for a good integrated circuit, a separation between bands for a good integrated circuit, a separation ratio between any two bands for a good integrated circuit, a maximum slope for a good band, a variation in a band width for a good band, a maximum IDDQ value for a chip, a minimum IDDQ value for a chip, a mean of a band of a chip, a standard deviation of a band of a chip, a lack of activity of IDDQ measurements conducted in the integrated circuit, noise in the IDDQ measurements conducted in the integrated circuit and glitches in the IDDQ measurements conducted in the integrated circuit. The parameters can be customized for the integrated circuit under test. The method and system can be used with all types of digital CMOS integrated circuits including integrated circuits with or without memories and deep submicron integrated circuits with or without memories.
摘要翻译： 本发明涉及一种用于检测集成电路中的缺陷的方法和系统，其中分类器的一个或多个参数通过IDDQ电流测量的图形评估来确定。 分类器的参数可以包括用于良好集成电路的多个频带，用于良好芯片的频带的宽度，用于良好集成电路的任何两个频带之间的宽度比，用于良好集成电路的频带之间的间隔， 用于良好集成电路的任何两个频带之间的分离比，良好频带的最大斜率，良好频带的带宽的变化，芯片的最大IDDQ值，芯片的最小IDDQ值，平均值 芯片的频带，芯片的频带的标准偏差，在集成电路中进行的IDDQ测量的缺乏活动，在集成电路中进行的IDDQ测量中的噪声和在集成电路中进行的IDDQ测量中的毛刺 。 可以为被测集成电路定制参数。 该方法和系统可用于所有类型的数字CMOS集成电路，包括具有或不具有存储器的集成电路和具有或不具有存储器的深亚微米集成电路。
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公开(公告)号：US5422891A
公开(公告)日：1995-06-06
申请号：US96731
申请日：1993-07-23
申请人： Michael L. Bushnell , Imtiaz Shaik
发明人： Michael L. Bushnell , Imtiaz Shaik
IPC分类号： G01R31/28 , G01R31/30 , G06F11/267 , G06F17/50
CPC分类号： G06F11/267 , G01R31/3016 , G06F2201/83 , G06F2201/88
摘要： This invention relates to a method and apparatus for robust delay fault testing of integrated circuits (IC) with built-in self-testing. For the method, hazardous nodes of the IC are determined. Thereafter, the topology of the IC can be modified to include a cut-point at hazardous nodes of the circuit. Input of the IC to the cut-point is diverted to an observation point. An out-put multi-input signature register (MISR) at the observation point generates a first signature. An output MISR provides a second signature for outputs to the IC. During testing, a hazard-free input pattern is applied to the IC and the generated first and second signatures are compared to known correct signatures.
摘要翻译： 本发明涉及一种具有内置自检功能的集成电路（IC）的鲁棒延迟故障测试方法和装置。 对于该方法，确定IC的危险节点。 此后，可以将IC的拓扑结构修改为在电路的危险节点处包含切点。 将IC输入到切点被转移到观察点。 在观察点的输出多输入签名寄存器（MISR）生成第一个签名。 输出MISR为IC的输出提供第二个签名。 在测试期间，将无危害的输入模式应用于IC，并将生成的第一和第二签名与已知的正确签名进行比较。
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