公开(公告)号：US07535297B2

公开(公告)日：2009-05-19

申请号：US11711292

申请日：2007-02-27

申请人： Xinghao Chen ,  Yanbo Tian ,  Norman Scheinberg

发明人： Xinghao Chen ,  Yanbo Tian ,  Norman Scheinberg

IPC分类号： H03G3/20

CPC分类号： H03G1/0088 ,  H03F1/0261 ,  H03F2200/27 ,  H03F2200/451 ,  H03F2200/456

摘要： An architecture and method for improving efficiency of a Class-A power amplifier by dynamically scaling biasing current thereof as well as synchronously compensating gain thereof in order to maintain overall constant gain of the Class-A power amplifier at all biasing configurations thereof. A biasing-current switching-network is operatively connected to the back-end block of the Class-A power amplifier. A gain-control switching-network is operatively connected to a front-end block of the Class-A power amplifier. A detector-and-control block is operatively connected to an output of the back-end block of the Class-A power amplifier, and samples a signal that is then compared with reference signals to determine switching configurations in the biasing-current switching-network and the gain-control switching network when the signal is processed through the front-end block of the Class-A power amplifier followed by the back-end block of the Class-A power amplifier. The biasing-current switching-network dynamically sets the back-end block biasing current of the Class-A power amplifier for a highest possible operating efficiency. The gain-control network simultaneously adjusts gain of the front-end block of the Class-A power amplifier to synchronize with a dynamic-biasing current-switching configuration to allow overall gain of the Class-A power amplifier to be constant in all biasing conditions.

摘要翻译： 一种用于通过动态地调整A类功率放大器的偏置电流以及同步补偿其增益来提高A类功率放大器的效率的架构和方法，以便在所有偏置配置下保持A类功率放大器的总体恒定增益。 偏置电流开关网络可操作地连接到A类功率放大器的后端模块。 增益控制交换网络可操作地连接到A类功率放大器的前端块。 检测器和控制块可操作地连接到A类功率放大器的后端块的输出，并且对与信号进行比较的信号进行采样，以确定偏置电流开关网络中的开关配置 以及增益控制交换网络，当信号通过A类功率放大器的前端块后跟A类功率放大器的后端块进行处理时。 偏置电流开关网络动态地设置A类功率放大器的后端块偏置电流，以实现最高的工作效率。 增益控制网络同时调节A类功率放大器的前端模块的增益，以与动态偏置电流切换配置同步，以使A类功率放大器的总体增益在所有偏置条件下保持恒定 。

公开(公告)号：US20100102825A1

公开(公告)日：2010-04-29

申请号：US12454476

申请日：2009-05-18

申请人： Michael L. Bushnell ,  Raghuveer Ausoori ,  Omar Khan ,  Deepak Mehta ,  Xinghao Chen

发明人： Michael L. Bushnell ,  Raghuveer Ausoori ,  Omar Khan ,  Deepak Mehta ,  Xinghao Chen

IPC分类号： G01R31/02 ,  G06F17/50 ,  H01R43/16

CPC分类号： G01R31/318583 ,  G06F17/505 ,  G06F2217/14 ,  Y10T29/49204

摘要： Design for testability (DFT) algorithms, which use both gradient descent and linear programming (LP) algorithms to insert test points (TPs) and/or scanned flip-flops (SFFs) into large circuits to make them testable are described. Scanning of either all flip-flops or a subset of flip-flops is supported. The algorithms measure testability using probabilities computed from logic simulation, Shannon's entropy measure (from information theory), and spectral analysis of the circuit in the frequency domain. The DFT hardware inserter methods uses toggling rates of the flip-flops (analyzed using digital signal processing (DSP) methods) and Shannon entropy measures of flip-flops to select flip-flops for scan. The optimal insertion of the DFT hardware reduces the amount of DFT hardware, since the gradient descent and linear program optimizations trade off inserting a TP versus inserting an SFF. The linear programs find the optimal solution to the optimization, and the entropy measures are used to maximize information flow through the circuit-under-test (CUT). The methods limit the amount of additional circuit hardware for test points and scan flip-flops.

摘要翻译： 描述了使用梯度下降和线性规划（LP）算法将测试点（TP）和/或扫描的触发器（SFF）插入大电路以使其可测试的可测性（DFT）算法的设计。 支持所有触发器或触发器子集的扫描。 该算法使用从逻辑仿真，香农熵测量（信息理论）和频域中的电路的频谱分析计算出的概率来测量可测性。 DFT硬件插入器方法使用触发器的转换速率（使用数字信号处理（DSP）方法分析））和触发器的Shannon熵测量来选择用于扫描的触发器。 DFT硬件的最佳插入减少了DFT硬件的数量，因为梯度下降和线性程序优化使插入TP与插入SFF成为交换。 线性程序找到优化的最优解，并且使用熵测量来最大化通过电路下测试（CUT）的信息流。 该方法限制了测试点和扫描触发器的附加电路硬件的数量。

公开(公告)号：US20090132882A1

公开(公告)日：2009-05-21

申请号：US12321170

申请日：2009-01-16

申请人： Xinghao Chen

发明人： Xinghao Chen

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/318536

摘要： A scan-load-based (SLB) dynamic scan configuration reconfigures scan structures via scan-load operation, thereby eliminating interconnect network distributing configuration signals, and employs common scan circuitry identical for designs at mask level and is suitable for ASIC implementations. The architecture includes reconfigurable scan cells, apparatus for distributing configuration data to the reconfigurable scan cells and for determining desired reconfiguration data for each of the reconfigurable scan cells, and a configuration-set (CS) signal. Each of the reconfigurable scan cells has a pass-through (PT) mode in which data input, either a scan-in (SI) or a system-data (SD) of the scan cell, is transparently passed to a scan-out (SO) terminal of the scan cell without requiring a pulse on a shift clock (SC). The configuration-set (CS) signal communicates with each of the reconfigurable scan cells. A pulse on the configuration-set (CS) signal triggers PT Hold latches to capture configuration data from corresponding slave latches, which in turn set configurations of each of the reconfigurable scan cells.

摘要翻译： 基于扫描负载（SLB）的动态扫描配置通过扫描加载操作重新配置扫描结构，从而消除互连网络分配配置信号，并采用与掩模级别相同的公共扫描电路，适用于ASIC实现。 该架构包括可重新配置的扫描单元，用于将配置数据分配到可重构扫描单元的装置，以及用于确定每个可重构扫描单元的所需重新配置数据以及配置集（CS）信号。 每个可重构扫描单元具有直通（PT）模式，其中扫描单元的扫描（SI）或系统数据（SD）的数据输入被透明地传递到扫描输出（ SO）端子，而不需要在移位时钟（SC）上的脉冲。 配置集（CS）信号与每个可重构扫描单元进行通信。 配置集（CS）信号上的一个脉冲触发PT Hold锁存器，从相应的从锁存器捕获配置数据，依次设置每个可重构扫描单元的配置。

公开(公告)号：US07702980B2

公开(公告)日：2010-04-20

申请号：US12321170

申请日：2009-01-16

申请人： Xinghao Chen

发明人： Xinghao Chen

IPC分类号： G01R31/28 ,  G06F11/00 ,  G11C19/00

CPC分类号： G01R31/318536

摘要： A scan-load-based (SLB) dynamic scan configuration reconfigures scan structures via scan-load operation, thereby eliminating interconnect network distributing configuration signals, and employs common scan circuitry identical for designs at mask level and is suitable for ASIC implementations. The architecture includes reconfigurable scan cells, apparatus for distributing configuration data to the reconfigurable scan cells and for determining desired reconfiguration data for each of the reconfigurable scan cells, and a configuration-set (CS) signal. Each of the reconfigurable scan cells has a pass-through (PT) mode in which data input, either a scan-in (SI) or a system-data (SD) of the scan cell, is transparently passed to a scan-out (SO) terminal of the scan cell without requiring a pulse on a shift clock (SC). The configuration-set (CS) signal communicates with each of the reconfigurable scan cells. A pulse on the configuration-set (CS) signal triggers PT Hold latches to capture configuration data from corresponding slave latches, which in turn set configurations of each of the reconfigurable scan cells.

摘要翻译： 基于扫描负载（SLB）的动态扫描配置通过扫描加载操作重新配置扫描结构，从而消除互连网络分配配置信号，并采用与掩模级别相同的公共扫描电路，适用于ASIC实现。 该架构包括可重新配置的扫描单元，用于将配置数据分配到可重构扫描单元的装置，以及用于确定每个可重构扫描单元的所需重新配置数据以及配置集（CS）信号。 每个可重构扫描单元具有直通（PT）模式，其中扫描单元的扫描（SI）或系统数据（SD）的数据输入被透明地传递到扫描输出（ SO）端子，而不需要在移位时钟（SC）上的脉冲。 配置集（CS）信号与每个可重构扫描单元进行通信。 配置集（CS）信号上的一个脉冲触发PT Hold锁存器，从相应的从锁存器捕获配置数据，依次设置每个可重构扫描单元的配置。

公开(公告)号：US20070200624A1

公开(公告)日：2007-08-30

申请号：US11711292

申请日：2007-02-27

申请人： Xinghao Chen ,  Yanbo Tian ,  Norman Scheinberg

发明人： Xinghao Chen ,  Yanbo Tian ,  Norman Scheinberg

IPC分类号： H03G3/20

CPC分类号： H03G1/0088 ,  H03F1/0261 ,  H03F2200/27 ,  H03F2200/451 ,  H03F2200/456

摘要： An architecture and method for improving efficiency of a Class-A power amplifier by dynamically scaling biasing current thereof as well as synchronously compensating gain thereof in order to maintain overall constant gain of the Class-A power amplifier at all biasing configurations thereof. A biasing-current switching-network is operatively connected to the back-end block of the Class-A power amplifier. A gain-control switching-network is operatively connected to a front-end block of the Class-A power amplifier. A detector-and-control block is operatively connected to an output of the back-end block of the Class-A power amplifier, and samples a signal that is then compared with reference signals to determine switching configurations in the biasing-current switching-network and the gain-control switching network when the signal is processed through the front-end block of the Class-A power amplifier followed by the back-end block of the Class-A power amplifier. The biasing-current switching-network dynamically sets the back-end block biasing current of the Class-A power amplifier for a highest possible operating efficiency. The gain-control network simultaneously adjusts gain of the front-end block of the Class-A power amplifier to synchronize with a dynamic-biasing current-switching configuration to allow overall gain of the Class-A power amplifier to be constant in all biasing conditions.

摘要翻译： 一种用于通过动态地调整A类功率放大器的偏置电流以及同步补偿其增益来提高A类功率放大器的效率的架构和方法，以便在所有偏置配置下保持A类功率放大器的总体恒定增益。 偏置电流开关网络可操作地连接到A类功率放大器的后端模块。 增益控制交换网络可操作地连接到A类功率放大器的前端块。 检测器和控制块可操作地连接到A类功率放大器的后端块的输出，并且对与信号进行比较的信号进行采样，以确定偏置电流开关网络中的开关配置 以及增益控制交换网络，当信号通过A类功率放大器的前端块后跟A类功率放大器的后端块进行处理时。 偏置电流开关网络动态地设置A类功率放大器的后端块偏置电流，以实现最高的工作效率。 增益控制网络同时调节A类功率放大器的前端模块的增益，以与动态偏置电流切换配置同步，以使A类功率放大器的总体增益在所有偏置条件下保持恒定 。

公开(公告)号：US08164345B2

公开(公告)日：2012-04-24

申请号：US12454476

申请日：2009-05-18

申请人： Michael L. Bushnell ,  Raghuveer Ausoori ,  Omar Khan ,  Deepak Mehta ,  Xinghao Chen

发明人： Michael L. Bushnell ,  Raghuveer Ausoori ,  Omar Khan ,  Deepak Mehta ,  Xinghao Chen

IPC分类号： G01R31/02 ,  G01R31/28 ,  G06F17/50

CPC分类号： G01R31/318583 ,  G06F17/505 ,  G06F2217/14 ,  Y10T29/49204

摘要： Design for testability (DFT) algorithms, which use both gradient descent and linear programming (LP) algorithms to insert test points (TPs) and/or scanned flip-flops (SFFs) into large circuits to make them testable are described. Scanning of either all flip-flops or a subset of flip-flops is supported. The algorithms measure testability using probabilities computed from logic simulation, Shannon's entropy measure (from information theory), and spectral analysis of the circuit in the frequency domain. The DFT hardware inserter methods uses toggling rates of the flip-flops (analyzed using digital signal processing (DSP) methods) and Shannon entropy measures of flip-flops to select flip-flops for scan. The optimal insertion of the DFT hardware reduces the amount of DFT hardware, since the gradient descent and linear program optimizations trade off inserting a TP versus inserting an SFF. The linear programs find the optimal solution to the optimization, and the entropy measures are used to maximize information flow through the circuit-under-test (CUT). The methods limit the amount of additional circuit hardware for test points and scan flip-flops.

摘要翻译： 描述了使用梯度下降和线性规划（LP）算法将测试点（TP）和/或扫描的触发器（SFF）插入大电路以使其可测试的可测性（DFT）算法的设计。 支持所有触发器或触发器子集的扫描。 该算法使用从逻辑仿真，香农熵测量（信息理论）和频域中的电路的频谱分析计算出的概率来测量可测性。 DFT硬件插入器方法使用触发器的转换速率（使用数字信号处理（DSP）方法分析））和触发器的Shannon熵测量来选择用于扫描的触发器。 DFT硬件的最佳插入减少了DFT硬件的数量，因为梯度下降和线性程序优化使插入TP与插入SFF成为交换。 线性程序找到优化的最优解，并且使用熵测量来最大化通过电路下测试（CUT）的信息流。 该方法限制了测试点和扫描触发器的附加电路硬件的数量。

公开(公告)号：US06922800B2

公开(公告)日：2005-07-26

申请号：US10654626

申请日：2003-09-03

申请人： Xinghao Chen ,  Joseph C. Watkins

发明人： Xinghao Chen ,  Joseph C. Watkins

IPC分类号： G11C29/10 ,  G11C29/00

CPC分类号： G11C29/10 ,  G11C8/16 ,  G11C2207/104

摘要： A method for improving the efficiency of test sequences for circuits with embedded multiple-port arrays, such as random access memory (RAM), is described, With existing test generation methods, it is a common occurrence that a resulting test sequence only utilizes a minimum number of read ports for detecting a target fault. When this type of test sequences is applied, one or more outputs of embedded RAMs may not attain known values, consequently reducing the effectiveness of the test sequences. The present invention enhances test sequences to that when they are applied, all outputs of embedded RAMs attain known values.

摘要翻译： 描述了一种用于提高具有嵌入式多端口阵列（例如随机存取存储器（RAM））的电路的测试序列的效率的方法。使用现有的测试生成方法，通常发生所得到的测试序列仅使用最小值 用于检测目标故障的读端口数。 当应用这种类型的测试序列时，嵌入式RAM的一个或多个输出可能不会获得已知值，因此降低了测试序列的有效性。 本发明将测试序列增强到应用时，嵌入式RAM的所有输出都达到已知值。

公开(公告)号：US06618826B1

公开(公告)日：2003-09-09

申请号：US09697362

申请日：2000-10-26

申请人： Xinghao Chen ,  Joseph C. Watkins

发明人： Xinghao Chen ,  Joseph C. Watkins

IPC分类号： G11C2900

CPC分类号： G11C29/10 ,  G11C8/16 ,  G11C2207/104

摘要： A method for improving the efficiency of test sequences for circuits with embedded multiple-port arrays, such as random access memory (RAM), is described. With existing test generation methods, it is a common occurrence that a resulting test sequence only utilizes a minimum number of read ports for detecting a target fault. When this type of test sequences is applied, one or more outputs of embedded RAMs may not attain known values, consequently reducing the effectiveness of the test sequences. The present invention enhances test sequences so that when they are applied, all outputs of embedded RAMs attain known values.

摘要翻译： 描述了一种用于提高具有嵌入式多端口阵列（诸如随机存取存储器（RAM））的电路的测试序列的效率的方法。 利用现有的测试生成方法，通常情况下，产生的测试序列仅利用最小数量的读取端口来检测目标故障。 当应用这种类型的测试序列时，嵌入式RAM的一个或多个输出可能不会获得已知值，因此降低了测试序列的有效性。 本发明增强测试序列，使得当它们被应用时，嵌入式RAM的所有输出都达到已知值。