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    Fast pipelined distributed arbitration scheme
    1.
    发明授权
    Fast pipelined distributed arbitration scheme 失效
    快速流水线分布仲裁方案

    公开(公告)号：US5519838A

    公开(公告)日：1996-05-21

    申请号：US201186

    申请日：1994-02-24

    申请人： Michael L. Ziegler ,  Robert J. Brooks ,  William R. Bryg ,  Kenneth K. Chan ,  Thomas R. Hotchkiss ,  Robert E. Naas ,  Robert D. Odineal ,  Brendan A. Voge ,  James B. Williams ,  John L. Wood

    发明人： Michael L. Ziegler ,  Robert J. Brooks ,  William R. Bryg ,  Kenneth K. Chan ,  Thomas R. Hotchkiss ,  Robert E. Naas ,  Robert D. Odineal ,  Brendan A. Voge ,  James B. Williams ,  John L. Wood

    IPC分类号： G06F13/368 ,  G06F13/00

    CPC分类号： G06F13/368

    摘要： A bus system having a bus arbitration scheme. The bus system includes a bus and a plurality of client modules coupled to the bus. Each of the client modules is capable of transmitting information on the bus to another of client module, and only one client module is entitled to transmit information on the bus at any time. A module entitled to transmit information on the bus has control of the bus for a minimum period of time defining a cycle. To determine which module is entitled to use the bus, each client module generates an arbitration signal when it seeks to transmit information on the bus. Each client module has an arbitration signal processor responsive to the arbitration signals for determining whether the module is entitled to transmit information on said bus. The system preferably also contains a host module that informs the client modules what types of transactions allowed on the bus in a given cycle. Each arbitration signal processor preferably is also responsive to the client option signals sent by the host module during an earlier cycle.

    摘要翻译： 具有总线仲裁方案的总线系统。 总线系统包括总线和耦合到总线的多个客户端模块。 每个客户端模块能够将总线上的信息发送到客户端模块的另一个，只有一个客户端模块有权在任何时候在总线上传输信息。 有权在总线上传输信息的模块可以控制总线最短时间来定义一个周期。 为了确定哪个模块有权使用总线，当客户端模块试图在总线上传输信息时，每个客户端模块都会产生仲裁信号。 每个客户端模块具有响应于仲裁信号的仲裁信号处理器，用于确定模块是否有权在所述总线上发送信息。 系统还优选地还包括主机模块，其向客户端模块通知在给定周期中在总线上允许的交易类型。 每个仲裁信号处理器优选地还响应于在较早的周期期间由主机模块发送的客户端选项信号。

    Method and apparatus for replacing cache lines in a cache memory
    5.
    发明授权
    Method and apparatus for replacing cache lines in a cache memory 失效
    用于替换高速缓冲存储器中的高速缓存行的方法和装置

    公开(公告)号：US06490654B2

    公开(公告)日：2002-12-03

    申请号：US09127491

    申请日：1998-07-31

    申请人： John A. Wickeraad ,  Stephen B. Lyle ,  Brendan A. Voge

    发明人： John A. Wickeraad ,  Stephen B. Lyle ,  Brendan A. Voge

    IPC分类号： G06F1212

    CPC分类号： G06F12/121 ,  G06F21/00

    摘要： A cache memory replacement algorithm replaces cache lines based on the likelihood that cache lines will not be needed soon. A cache memory in accordance with the present invention includes a plurality of cache lines that are accessed associatively, with a count entry associated with each cache line storing a count value that defines a replacement class. The count entry is typically loaded with a count value when the cache line is accessed, with the count value indicating the likelihood that the contents of cache lines will be needed soon. In other words, data which is likely to be needed soon is assigned a higher replacement class, while data that is more speculative and less likely to be needed soon is assigned a lower replacement class. When the cache memory becomes full, the replacement algorithm selects for replacement those cache lines having the lowest replacement class. Accordingly, the cache lines selected for replacement contain the most speculative data in the cache that is least likely to be needed soon.

    摘要翻译： 高速缓存存储器替换算法基于不久之后不需要高速缓存行的可能性来替换高速缓存行。 根据本发明的高速缓冲存储器包括多个高速缓存行，其被相关联地访问，与存储定义替换类的计数值的每个高速缓存行相关联的计数条目。 当访问高速缓存行时，计数条目通常加载计数值，其中计数值指示即将需要高速缓存行内容的可能性。 换句话说，很快可能需要的数据被分配更高的替换类，而更具有推测性且不太可能需要的数据被分配较低的替换类。 当高速缓冲存储器变满时，替换算法选择替换具有最低替换类的那些高速缓存行。 因此，选择用于替换的高速缓存行包含尽快不太可能需要的高速缓存中最具推测性的数据。