公开(公告)号：US5923370A

公开(公告)日：1999-07-13

申请号：US726827

申请日：1996-10-08

申请人： Michael Miethig ,  Charles Russell Smith ,  Eric Charles Fox ,  Michael George Farrier

发明人： Michael Miethig ,  Charles Russell Smith ,  Eric Charles Fox ,  Michael George Farrier

IPC分类号： H01L27/148 ,  H04N5/357 ,  H04N5/359 ,  H04N5/361 ,  H04N5/3722 ,  H04N5/217 ,  H04N3/14

CPC分类号： H04N5/3722 ,  H04N5/3595 ,  H04N5/361

摘要： A fast frame interline transfer charge coupled device imaging sensor includes an imaging section and an storage section. The imaging section includes a plurality of interline transfer registers, each interline transfer register containing a plurality of interline register elements. The imaging section further includes an interline clocking structure, the interline clocking structure including polycrystalline silicon buss lines used as gate electrodes, the polycrystalline silicon buss lines being connected to a metal strapping network, the interline clocking structure causing charge to be transferred between interline register elements of each interline transfer register based on interline clocking signals. The storage section is coupled to the imaging section. The storage section includes a plurality of storage registers, each storage register containing a plurality of storage register elements. The storage section further includes a storage discharge structure and a storage clocking structure. Each storage register element of the storage registers is selectively coupleable through the storage discharge structure to a storage drain. The storage clocking structure has first and second clocking structure parts, the first clocking structure part corresponding to first storage register elements coupled to respective interline registers. The first clocking structure part is coupled to the interline clocking structure so as to cause charge to be transferred from the respective interline registers to the first storage register elements based on the interline clocking signals. The second clocking structure part causes charge to be transferred between storage register elements of each storage register based on frame clocking signals.

摘要翻译： 快速帧间线传输电荷耦合器件成像传感器包括成像部分和存储部分。 成像部分包括多个行间传送寄存器，每个行间传送寄存器包含多个行间寄存器元件。 所述成像部分还包括行间时钟结构，所述行间时钟结构包括用作栅电极的多晶硅总线，所述多晶硅总线连接到金属捆绑网络，所述行间时钟结构使得电荷在线间寄存器元件 基于行间时钟信号的每个行间传送寄存器。 存储部分耦合到成像部分。 存储部分包括多个存储寄存器，每个存储寄存器包含多个存储寄存器元件。 存储部还包括存储放电结构和存储时钟结构。 存储寄存器的每个存储寄存器元件通过存储放电结构选择性地耦合到存储器漏极。 存储时钟结构具有第一和第二时钟结构部分，第一时钟结构部分对应于耦合到相应行间寄存器的第一存储寄存器元件。 第一时钟结构部分耦合到行间时钟结构，以便基于行间时钟信号使电荷从相应的行间寄存器传送到第一存储寄存器元件。 第二时钟结构部分基于帧时钟信号使得在每个存储寄存器的存储寄存器元件之间传送电荷。

公开(公告)号：US06847070B2

公开(公告)日：2005-01-25

申请号：US10338738

申请日：2003-01-09

申请人： Eric Charles Fox

发明人： Eric Charles Fox

IPC分类号： H01L29/04 ,  H01L31/062

CPC分类号： H04N5/3745 ,  H04N5/3594

摘要： A method of sensing radiation in a pixel includes applying a transfer clock signal, applying a pixel reset clock signal, and applying a pixel reset voltage. The applying a transfer clock signal applies the transfer clock signal to a gate electrode of a transfer gate transistor. The applying a pixel reset clock signal applies the pixel reset clock signal to a gate electrode of the pixel reset transistor. The applying a pixel reset voltage applies the pixel reset voltage to a drain of the pixel reset transistor. The method further includes switching the transfer clock signal to a high state, switching the pixel reset clock signal to a high state, switching the pixel reset voltage to a low state, switching the pixel reset voltage to a high state, and switching the pixel reset clock signal to a low state at a beginning of an integration cycle.

摘要翻译： 感测像素中的辐射的方法包括施加传输时钟信号，应用像素复位时钟信号，以及应用像素复位电压。 施加传送时钟信号将传送时钟信号施加到传输门晶体管的栅电极。 施加像素复位时钟信号将像素复位时钟信号施加到像素复位晶体管的栅电极。 施加像素复位电压将像素复位电压施加到像素复位晶体管的漏极。 该方法还包括将传输时钟信号切换到高状态，将像素复位时钟信号切换到高状态，将像素复位电压切换到低状态，将像素复位电压切换到高状态，并切换像素复位 时钟信号在积分周期开始时处于低电平状态。

公开(公告)号：US07045753B1

公开(公告)日：2006-05-16

申请号：US10434285

申请日：2003-05-09

申请人： Eric Charles Fox

发明人： Eric Charles Fox

IPC分类号： H01L27/00

CPC分类号： H04N5/3745 ,  H04N5/3592 ,  H04N5/365

摘要： A pixel includes five transistors, a photodetector and a storage node. A first transistor is coupled between the photodetector and the storage node. A second transistor includes a second transistor source and a second transistor drain. The second transistor source is coupled to the storage node. The second transistor drain is coupled to an output drain voltage. A third transistor includes a third transistor drain. The third transistor is coupled between the photodetector and a pixel reset voltage. The third transistor drain is coupled to the pixel reset voltage. The pixel reset voltage is different than the output drain voltage.

摘要翻译： 像素包括五个晶体管，光电检测器和存储节点。 第一晶体管耦合在光电检测器和存储节点之间。 第二晶体管包括第二晶体管源极和第二晶体管漏极。 第二晶体管源耦合到存储节点。 第二晶体管漏极耦合到输出漏极电压。 第三晶体管包括第三晶体管漏极。 第三晶体管耦合在光电检测器和像素复位电压之间。 第三晶体管漏极耦合到像素复位电压。 像素复位电压不同于输出漏极电压。