公开(公告)号：US07943928B2

公开(公告)日：2011-05-17

申请号：US11603340

申请日：2006-11-21

申请人： Michael Runde ,  Gernot Langguth ,  Klaus Roeschlau ,  Karlheinz Mueller

发明人： Michael Runde ,  Gernot Langguth ,  Klaus Roeschlau ,  Karlheinz Mueller

IPC分类号： H01L29/04

CPC分类号： H01L27/0255 ,  H01L29/861

摘要： An ESD protection structure includes a structure to be protected disposed in a semiconductor body. A region of a first conductivity type is disposed within the semiconductor body and a channel is disposed in the semiconductor body and extends through the region of the first conductivity type. A semiconductor of a second conductivity type is disposed within the channel adjacent the region of the first conductivity type such that the region of the first conductivity type and the semiconductor of the second conductivity type form a diode. At least one of the region of the first conductivity type and the semiconductor of the second conductivity type is electrically coupled to the structure to be protected.

摘要翻译： ESD保护结构包括被配置在半导体本体中的要被保护的结构。 第一导电类型的区域设置在半导体本体内，并且沟道设置在半导体本体中并且延伸穿过第一导电类型的区域。 第二导电类型的半导体设置在与第一导电类型的区域相邻的沟道内，使得第一导电类型的区域和第二导电类型的半导体形成二极管。 第一导电类型的区域和第二导电类型的半导体中的至少一个电耦合到待保护的结构。

公开(公告)号：US20080035924A1

公开(公告)日：2008-02-14

申请号：US11603340

申请日：2006-11-21

申请人： Michael Runde ,  Gernot Langguth ,  Klaus Roeschlau ,  Karlheinz Mueller

发明人： Michael Runde ,  Gernot Langguth ,  Klaus Roeschlau ,  Karlheinz Mueller

IPC分类号： H01L29/04

CPC分类号： H01L27/0255 ,  H01L29/861

摘要： An ESD protection structure includes a structure to be protected disposed in a semiconductor body. A region of a first conductivity type is disposed within the semiconductor body and a channel is disposed in the semiconductor body and extends through the region of the first conductivity type. A semiconductor of a second conductivity type is disposed within the channel adjacent the region of the first conductivity type such that the region of the first conductivity type and the semiconductor of the second conductivity type form a diode. At least one of the region of the first conductivity type and the semiconductor of the second conductivity type is electrically coupled to the structure to be protected.

摘要翻译： ESD保护结构包括被配置在半导体本体中的要被保护的结构。 第一导电类型的区域设置在半导体本体内，并且沟道设置在半导体本体中并且延伸穿过第一导电类型的区域。 第二导电类型的半导体设置在与第一导电类型的区域相邻的沟道内，使得第一导电类型的区域和第二导电类型的半导体形成二极管。 第一导电类型的区域和第二导电类型的半导体中的至少一个电耦合到待保护的结构。

公开(公告)号：US08021952B2

公开(公告)日：2011-09-20

申请号：US12503505

申请日：2009-07-15

申请人： Karlheinz Mueller ,  Klaus Roeschlau

发明人： Karlheinz Mueller ,  Klaus Roeschlau

IPC分类号： H01L21/331

CPC分类号： H01L29/0649 ,  H01L21/2257 ,  H01L29/732 ,  H01L29/7809

摘要： Integrated transistor and method for the production is disclosed. An explanation is given of, inter alia, a transistor having an electrically insulating isolating trench extending from a main area in the direction of a connection region remote from the main area. Moreover, the transistor contains an auxiliary trench extending from the main area as far as the connection region remote from the main area. The transistor requires a small chip area and has outstanding electrical properties.

摘要翻译： 公开了用于生产的集成晶体管和方法。 具体来说，说明了具有从远离主区域的连接区域的方向从主区域延伸的电绝缘隔离沟道的晶体管。 此外，晶体管包括从主区域延伸到远离主区域的连接区域的辅助沟槽。 晶体管需要小的芯片面积并具有出色的电气特性。

公开(公告)号：US08129249B2

公开(公告)日：2012-03-06

申请号：US12878377

申请日：2010-09-09

申请人： Karlheinz Mueller ,  Klaus Roeschlau

发明人： Karlheinz Mueller ,  Klaus Roeschlau

IPC分类号： H01L21/331

CPC分类号： H01L29/0649 ,  H01L21/2257 ,  H01L29/732 ,  H01L29/7809

摘要： Integrated transistor and method for the production is disclosed. An explanation is given of, inter alia, a transistor having an electrically insulating isolating trench extending from a main area in the direction of a connection region remote from the main area. Moreover, the transistor contains an auxiliary trench extending from the main area as far as the connection region remote from the main area. The transistor requires a small chip area and has outstanding electrical properties.

摘要翻译： 公开了用于生产的集成晶体管和方法。 具体来说，说明了具有从远离主区域的连接区域的方向从主区域延伸的电绝缘隔离沟道的晶体管。 此外，晶体管包括从主区域延伸到远离主区域的连接区域的辅助沟槽。 该晶体管需要小的芯片面积并具有出色的电气特性。

公开(公告)号：US20070023865A1

公开(公告)日：2007-02-01

申请号：US11486748

申请日：2006-07-14

申请人： Karlheinz Mueller ,  Klaus Roeschlau

发明人： Karlheinz Mueller ,  Klaus Roeschlau

IPC分类号： H01L27/082

CPC分类号： H01L29/0649 ,  H01L21/2257 ,  H01L29/732 ,  H01L29/7809

摘要： Integrated transistor and method for the production is disclosed. An explanation is given of, inter alia, a transistor having an electrically insulating isolating trench extending from a main area in the direction of a connection region remote from the main area. Moreover, the transistor contains an auxiliary trench extending from the main area as far as the connection region remote from the main area. The transistor requires a small chip area and has outstanding electrical properties.

摘要翻译： 公开了用于生产的集成晶体管和方法。 具体来说，说明了具有从远离主区域的连接区域的方向从主区域延伸的电绝缘隔离沟道的晶体管。 此外，晶体管包括从主区域延伸到远离主区域的连接区域的辅助沟槽。 该晶体管需要小的芯片面积并具有出色的电气特性。

公开(公告)号：US09048096B2

公开(公告)日：2015-06-02

申请号：US11844965

申请日：2007-08-24

申请人： Jens Schneider ,  Klaus Roeschlau ,  Harald Gossner

发明人： Jens Schneider ,  Klaus Roeschlau ,  Harald Gossner

IPC分类号： H01L23/62 ,  H01L27/02

CPC分类号： H01L27/0259 ,  H01L27/0255 ,  H01L29/0684 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/732 ,  H01L29/7833 ,  H02H9/041

摘要： The invention relates to an ESD protection circuit for an integrated circuit including a drain-extended MOS device and an output pad that requires protection. The ESD protection circuit includes a first diode coupled to the output pad and to a bias voltage rail, a second diode coupled to the output pad and to another bias voltage rail, and an ESD power clamp coupled between the two bias voltage rails. The ESD power clamp is formed as a vertical npn transistor with its base and emitter coupled together. The collector of the npn transistor is formed using an n-well implantation and a DEMOS n-drain extension to produce a snapback-based voltage limiting characteristic. The diodes are formed with a lightly p-doped substrate region over a buried n-type layer, and a p-well implant and an n-well implant separated by intervening substrate. A third diode may be coupled between the two bias voltage rails.

摘要翻译： 本发明涉及一种用于集成电路的ESD保护电路，其包括需要保护的漏极扩展MOS器件和输出焊盘。 ESD保护电路包括耦合到输出焊盘和偏置电压轨道的第一二极管，耦合到输出焊盘和另一个偏置电压轨道的第二二极管，以及耦合在两个偏置电压轨道之间的ESD功率钳位。 ESD功率钳位形成为垂直的npn晶体管，其基极和发射极耦合在一起。 npn晶体管的集电极使用n阱注入和DEMOS n漏极扩展形成，以产生基于快速恢复的电压限制特性。 二极管由掩埋的n型层上的轻掺杂p型衬底区域和由插入衬底分离的p阱注入和n阱注入形成。 第三二极管可以耦合在两个偏置电压轨道之间。

公开(公告)号：US20090050970A1

公开(公告)日：2009-02-26

申请号：US11844965

申请日：2007-08-24

申请人： Jens Schneider ,  Klaus Roeschlau ,  Harald Gossner

发明人： Jens Schneider ,  Klaus Roeschlau ,  Harald Gossner

IPC分类号： H01L23/62 ,  H01L21/8249

CPC分类号： H01L27/0259 ,  H01L27/0255 ,  H01L29/0684 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/732 ,  H01L29/7833 ,  H02H9/041

摘要： The invention relates to an ESD protection circuit for an integrated circuit including a drain-extended MOS device and an output pad that requires protection. The ESD protection circuit includes a first diode coupled to the output pad and to a bias voltage rail, a second diode coupled to the output pad and to another bias voltage rail, and an ESD power clamp coupled between the two bias voltage rails. The ESD power clamp is formed as a vertical npn transistor with its base and emitter coupled together. The collector of the npn transistor is formed using an n-well implantation and a DEMOS n-drain extension to produce a snapback-based voltage limiting characteristic. The diodes are formed with a lightly p-doped substrate region over a buried n-type layer, and a p-well implant and an n-well implant separated by intervening substrate. A third diode may be coupled between the two bias voltage rails.

摘要翻译： 本发明涉及一种用于集成电路的ESD保护电路，其包括需要保护的漏极扩展MOS器件和输出焊盘。 ESD保护电路包括耦合到输出焊盘和偏置电压轨道的第一二极管，耦合到输出焊盘和另一个偏置电压轨道的第二二极管，以及耦合在两个偏置电压轨道之间的ESD功率钳位。 ESD功率钳位形成为垂直的npn晶体管，其基极和发射极耦合在一起。 npn晶体管的集电极使用n阱注入和DEMOS n漏极扩展形成，以产生基于快速恢复的电压限制特性。 二极管由掩埋的n型层上的轻掺杂p型衬底区域和由插入衬底分离的p阱注入和n阱注入形成。 第三二极管可以耦合在两个偏置电压轨道之间。