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1.发明申请Internally Controlling and Enhancing Logic Built-In Self Test in a Multiple Core Microprocessor 失效在多核微处理器中内部控制和增强逻辑内置自检公开(公告)号：US20100262879A1
公开(公告)日：2010-10-14
申请号：US12423442
申请日：2009-04-14
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/3187 , G01R31/31724 , G06F11/27
摘要： A mechanism is provided for internally controlling and enhancing logic built-in self test in a multiple core microprocessor. The control core may use architectural support for scan and external scan communication (XSCOM) to independently test the other cores while adjusting their frequency and/or voltage. A program loaded onto the control core may adjust the frequency and configure the LBIST to run on each of the cores under test. Once LBIST has completed on a core under test, the control core's program may evaluate the results and decide a next test to run for that core. For isolating failing latch positions, the control core may iteratively configure the LBIST mask and sequence registers on the core under test to determine the location of the failing latch. The control core may control the LBIST stump masks to isolate the failure to a particular latch scan ring and then position within that ring.
摘要翻译： 提供了一种用于在多核微处理器内部控制和增强逻辑内置自检的机制。 控制核心可以使用架构支持扫描和外部扫描通信（XSCOM）来独立测试其他内核，同时调整其频率和/或电压。 加载到控制核心上的程序可以调整频率并配置LBIST以在被测试的每个核心上运行。 一旦LBIST已经在被测核心上完成，控制核心的程序可以评估结果并决定下一个测试以运行该核心。 为了隔离失效的锁存位置，控制核可以迭代地配置待测核心上的LBIST掩码和序列寄存器，以确定故障锁存器的位置。 控制核心可以控制LBIST残端掩模以将故障隔离到特定的锁存扫描环，然后位于该环内。
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2.发明授权Internally controlling and enhancing logic built-in self test in a multiple core microprocessor 失效在多核微处理器中内部控制和增强逻辑内置自检公开(公告)号：US08122312B2
公开(公告)日：2012-02-21
申请号：US12423442
申请日：2009-04-14
IPC分类号： G01R31/28
CPC分类号： G01R31/3187 , G01R31/31724 , G06F11/27
摘要： A mechanism is provided for internally controlling and enhancing logic built-in self test in a multiple core microprocessor. The control core may use architectural support for scan and external scan communication (XSCOM) to independently test the other cores while adjusting their frequency and/or voltage. A program loaded onto the control core may adjust the frequency and configure the LBIST to run on each of the cores under test. Once LBIST has completed on a core under test, the control core's program may evaluate the results and decide a next test to run for that core. For isolating failing latch positions, the control core may iteratively configure the LBIST mask and sequence registers on the core under test to determine the location of the failing latch. The control core may control the LBIST stump masks to isolate the failure to a particular latch scan ring and then position within that ring.
摘要翻译： 提供了一种用于在多核微处理器内部控制和增强逻辑内置自检的机制。 控制核心可以使用架构支持扫描和外部扫描通信（XSCOM）来独立测试其他内核，同时调整其频率和/或电压。 加载到控制核心上的程序可以调整频率并配置LBIST以在被测试的每个核心上运行。 一旦LBIST已经在被测核心上完成，控制核心的程序可以评估结果并决定下一个测试以运行该核心。 为了隔离失效的锁存位置，控制核可以迭代地配置待测核心上的LBIST掩码和序列寄存器，以确定故障锁存器的位置。 控制核心可以控制LBIST残端掩模以将故障隔离到特定的锁存扫描环，然后位于该环内。
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3.发明申请公开(公告)号：US20100122116A1
公开(公告)日：2010-05-13
申请号：US12269490
申请日：2008-11-12
IPC分类号： G06F11/07
CPC分类号： G06F11/2242
摘要： A mechanism is provided for internally controlling and enhancing advanced test and characterization in a multiple core microprocessor. To decrease the time needed to test a multiple core chip, the mechanism uses micro-architectural support that allows one core, a control core, to run a functional program to test the other cores. Any core on the chip can be designated to be the control core as long as it has already been tested for functionality at one safe frequency and voltage operating point. An external testing device loads a small program into the control core's dedicated memory. The program functionally running on the control core uses micro-architectural support for functional scan and external scan communication to independently test the other cores while adjusting the frequencies and/or voltages of the other cores until failure. The control core may independently test the other cores by starting, stopping, and determining pass/fail results.
摘要翻译： 提供了一种用于内部控制和增强多核微处理器中的高级测试和表征的机制。 为了减少测试多核芯片所需的时间，该机制使用微架构支持，允许一个核心（控制核心）运行功能程序来测试其他内核。 只要在一个安全频率和电压工作点已经测试了功能，芯片上的任何内核都可以被指定为控制核心。 外部测试设备将一个小程序加载到控制核心的专用存储器中。 在控制核心上运行的程序使用微架构支持功能扫描和外部扫描通信，以独立测试其他内核，同时调整其他内核的频率和/或电压直到故障。 控制核心可以通过启动，停止和确定通过/失败结果来独立测试其他内核。
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4.发明授权公开(公告)号：US08140902B2
公开(公告)日：2012-03-20
申请号：US12269490
申请日：2008-11-12
IPC分类号： G06F11/00
CPC分类号： G06F11/2242
摘要： A mechanism is provided for internally controlling and enhancing advanced test and characterization in a multiple core microprocessor. To decrease the time needed to test a multiple core chip, the mechanism uses micro-architectural support that allows one core, a control core, to run a functional program to test the other cores. Any core on the chip can be designated to be the control core as long as it has already been tested for functionality at one safe frequency and voltage operating point. An external testing device loads a small program into the control core's dedicated memory. The program functionally running on the control core uses micro-architectural support for functional scan and external scan communication to independently test the other cores while adjusting the frequencies and/or voltages of the other cores until failure. The control core may independently test the other cores by starting, stopping, and determining pass/fail results.
摘要翻译： 提供了一种用于内部控制和增强多核微处理器中的高级测试和表征的机制。 为了减少测试多核芯片所需的时间，该机制使用微架构支持，允许一个核心（控制核心）运行功能程序来测试其他内核。 只要在一个安全频率和电压工作点已经测试了功能，芯片上的任何内核都可以被指定为控制核心。 外部测试设备将一个小程序加载到控制核心的专用存储器中。 在控制核心上运行的程序使用微架构支持功能扫描和外部扫描通信，以独立测试其他内核，同时调整其他内核的频率和/或电压直到故障。 控制核心可以通过启动，停止和确定通过/失败结果来独立测试其他内核。
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5.发明申请公开(公告)号：US20090254788A1
公开(公告)日：2009-10-08
申请号：US12061752
申请日：2008-04-03
IPC分类号： G01R31/28
CPC分类号： G01R31/318335 , G01R31/3187 , G11C29/12015 , G11C29/16 , G11C29/44 , G11C2029/0405 , G11C2029/3202
摘要： A method, system and computer program product for performing real-time LBIST diagnostics of IC devices. During LBIST, stump data and identifiers of test cycles are saved in the IC device-under-test (DUT). If compressed stump data does not match a pre-defined coded value (i.e., “signature” of the test cycle), the saved stump data and an identifier of the failed test cycle are preserved, otherwise the determination is made the DUT passed the test cycle. Identifiers and stump of the failed test cycles are used to analyze errors, including virtually non-reproducible errors.
摘要翻译： 一种用于执行IC器件实时LBIST诊断的方法，系统和计算机程序产品。 在LBIST期间，残留数据和测试周期的标识符保存在IC器件中（DUT）中。 如果压缩树桩数据与预定义的编码值（即测试周期的“签名”）不匹配，则保存的桩号数据和故障测试周期的标识符被保留，否则确定DUT通过测试 周期。 故障测试周期的标识符和残差用于分析错误，包括几乎不可重现的错误。
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6.发明申请公开(公告)号：US20090132983A1
公开(公告)日：2009-05-21
申请号：US12271588
申请日：2008-11-14
申请人： Robert B. Gass , Yee Ja , Christoph Jaeschke
发明人： Robert B. Gass , Yee Ja , Christoph Jaeschke
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： An apparatus and computer program product for driving values to “don't care” (DC) adjusted/untimed nets of an integrated circuit design to thereby identify timing problems are provided. The apparatus and computer program product may be utilized, for example, with logical built-in self test (LBIST) testing of an integrated circuit in which the DC adjusted (dcadj) nets for normal functional mode of the integrated circuit may not be DC adjusted for LBIST mode. By using the apparatus and computer program product, timing related problems associated with DC adjusted/untimed nets can be made apparent either by using simulation or semi-formal/formal analysis. For example, with regard to DC adjusted/untimed nets, the apparatus and computer program product may identify any violations of these nets with regard to maintaining their DC adjusted values. Such identification of violations of DC adjusted/untimed nets may be made without interfering with the static timing analysis of timed nets.
摘要翻译： 提供了一种用于驱动集成电路设计的“无关心”（DC）调整/未定型网络的值的装置和计算机程序产品，从而识别定时问题。 该装置和计算机程序产品可以用于例如集成电路的逻辑内置自检（LBIST）测试，其中用于集成电路的正常功能模式的DC调节（dcadj）网络可能不被直流调整 用于LBIST模式。 通过使用设备和计算机程序产品，可以通过使用模拟或半正式/形式分析，使与DC调整/未定义网相关的定时相关问题变得明显。 例如，关于DC调整/未定义的网络，设备和计算机程序产品可以识别关于维持其DC调整值的任何这些网络的违规。 可以在不干扰定时网络的静态时序分析的情况下进行对DC调整/未定义网的违规的识别。
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7.发明授权Method for driving values to DC adjusted/untimed nets to identify timing problems 失效将值驱动到DC调整/未定义网络以识别时序问题的方法公开(公告)号：US07490305B2
公开(公告)日：2009-02-10
申请号：US11457865
申请日：2006-07-17
申请人： Robert B. Gass , Yee Ja , Christoph Jaeschke
发明人： Robert B. Gass , Yee Ja , Christoph Jaeschke
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method for driving values to “don't care” (DC) adjusted/untimed nets of an integrated circuit design to thereby identify timing problems are provided. The system and method may be utilized, for example, with logical built-in self test (LBIST) testing of an integrated circuit in which the DC adjusted (dcadj) nets for normal functional mode of the integrated circuit may not be DC adjusted for LBIST mode. By using the system and method, timing related problems associated with DC adjusted/untimed nets can be made apparent either by using simulation or semi-formal/formal analysis. For example, with regard to DC adjusted/untimed nets, the system and method may identify any violations of these nets with regard to maintaining their DC adjusted values. Such identification of violations of DC adjusted/untimed nets may be made without interfering with the static timing analysis of timed nets.
摘要翻译： 提供了一种用于驱动集成电路设计的“不关心”（DC）调整/未定网的值从而识别定时问题的方法。 该系统和方法可以用于例如集成电路的逻辑内置自检（LBIST）测试，其中用于集成电路的正常功能模式的DC调节（dcadj）网络可以不被LB调整为LBIST 模式。 通过使用系统和方法，通过使用模拟或半正规/形式分析，可以使与DC调整/未定义网相关的定时相关问题变得明显。 例如，关于DC调整/未定义的网络，系统和方法可以识别关于维持其DC调整值的任何这些网络的违规。 可以在不干扰定时网络的静态时序分析的情况下进行对DC调整/未定义网的违规的识别。
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8.发明授权Automated system and processing for expedient diagnosis of broken shift registers latch chains 有权自动化系统和处理方便诊断破碎的移位寄存器锁链公开(公告)号：US07908532B2
公开(公告)日：2011-03-15
申请号：US12032655
申请日：2008-02-16
IPC分类号： G01R31/28
CPC分类号： G01R31/318544 , G01R31/318536
摘要： This invention involves the use of the JTAG functional test patterns and exercisors to solve the problem of diagnosing broken scan chains in either a serial or a lateral broadside insertion manner across all latch system ports and to analyze the response data efficiently for the purpose of readily identifying switching and non-switching latches with the next to last non-switching latch being the point of the break within a defective scan chain(s). This comprehensive latch perturbation, in conjunction with iterative diagnostic algorithms is used to identify and to pinpoint the defective location in such a broken scan chain(s). This JTAG Functional test function and the JTAG test patterns ultimately derived therefrom, can take on different forms and origins, some external to a product and some internal to a product.
摘要翻译： 本发明涉及使用JTAG功能测试模式和执行者来解决在所有锁存系统端口中以串行或侧向宽边插入方式诊断断层扫描链的问题，并且有效地分析响应数据以便容易地识别 切换和非切换锁存器与下一个最后一个非切换锁存器是故障扫描链中的断点。 这种综合的锁定扰动结合迭代诊断算法用于识别并确定在这种断开的扫描链中的有缺陷的位置。 这种JTAG功能测试功能和最终从其导出的JTAG测试模式可以承载不同的形式和起源，一些产品外部和产品内部。
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9.发明授权公开(公告)号：US07886244B2
公开(公告)日：2011-02-08
申请号：US12271588
申请日：2008-11-14
申请人： Robert B. Gass , Yee Ja , Christoph Jaeschke
发明人： Robert B. Gass , Yee Ja , Christoph Jaeschke
CPC分类号： G06F17/5031
摘要： An apparatus and computer program product for driving values to “don't care” (DC) adjusted/untimed nets of an integrated circuit design to thereby identify timing problems are provided. The apparatus and computer program product may be utilized, for example, with logical built-in self test (LBIST) testing of an integrated circuit in which the DC adjusted (dcadj) nets for normal functional mode of the integrated circuit may not be DC adjusted for LBIST mode. By using the apparatus and computer program product, timing related problems associated with DC adjusted/untimed nets can be made apparent either by using simulation or semi-formal/formal analysis. For example, with regard to DC adjusted/untimed nets, the apparatus and computer program product may identify any violations of these nets with regard to maintaining their DC adjusted values. Such identification of violations of DC adjusted/untimed nets may be made without interfering with the static timing analysis of timed nets.
摘要翻译： 提供了一种用于驱动集成电路设计的“无关心”（DC）调整/未定型网络的值的装置和计算机程序产品，从而识别定时问题。 该装置和计算机程序产品可以用于例如集成电路的逻辑内置自检（LBIST）测试，其中用于集成电路的正常功能模式的DC调节（dcadj）网络可能不被直流调整 用于LBIST模式。 通过使用设备和计算机程序产品，可以通过使用模拟或半正式/形式分析，使与DC调整/未定义网相关的定时相关问题变得明显。 例如，关于DC调整/未定义的网络，设备和计算机程序产品可以识别关于维持其DC调整值的任何这些网络的违规。 可以在不干扰定时网络的静态时序分析的情况下进行对DC调整/未定义网的违规的识别。
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10.发明申请System and Method for Driving Values to DC Adjusted/Untimed Nets to Identify Timing Problems 失效用于向直流调整/无源网络驱动价值以识别时序问题的系统和方法公开(公告)号：US20080016480A1
公开(公告)日：2008-01-17
申请号：US11457865
申请日：2006-07-17
申请人： Robert B. Gass , Yee Ja , Christoph Jaeschke
发明人： Robert B. Gass , Yee Ja , Christoph Jaeschke
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A system and method for driving values to “don't care” (DC) adjusted/untimed nets of an integrated circuit design to thereby identify timing problems are provided. The system and method may be utilized, for example, with logical built-in self test (LBIST) testing of an integrated circuit in which the DC adjusted (dcadj) nets for normal functional mode of the integrated circuit may not be DC adjusted for LBIST mode. By using the system and method, timing related problems associated with DC adjusted/untimed nets can be made apparent either by using simulation or semi-formal/formal analysis. For example, with regard to DC adjusted/untimed nets, the system and method may identify any violations of these nets with regard to maintaining their DC adjusted values. Such identification of violations of DC adjusted/untimed nets may be made without interfering with the static timing analysis of timed nets.
摘要翻译： 提供了一种用于驱动集成电路设计的“无关心”（DC）调整/未定型网络的值以便识别定时问题的系统和方法。 该系统和方法可以用于例如集成电路的逻辑内置自检（LBIST）测试，其中用于集成电路的正常功能模式的DC调节（dcadj）网络可以不被LB调整为LBIST 模式。 通过使用系统和方法，通过使用模拟或半正规/形式分析，可以使与DC调整/未定义网相关的定时相关问题变得明显。 例如，关于DC调整/未定义的网络，系统和方法可以识别关于维持其DC调整值的任何这些网络的违规。 可以在不干扰定时网络的静态时序分析的情况下进行对DC调整/未定义网的违规的识别。
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