公开(公告)号：US20080127010A1

公开(公告)日：2008-05-29

申请号：US11563704

申请日：2006-11-28

申请人： Michael W. Beattie ,  Kevin Beattie ,  Byron L. Krauter ,  Hui Zheng

发明人： Michael W. Beattie ,  Kevin Beattie ,  Byron L. Krauter ,  Hui Zheng

IPC分类号： G06F17/50

CPC分类号： G06F17/5009 ,  G06F17/5036 ,  G06F2217/40 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/0401

摘要： A computer implemented method, data processing system, and computer usable program code are provided for reducing a chip package model. Responsive to receiving the chip package model, an inductance and a resistance of the chip package model is measured. The inductance and the resistance are measured using only a set of external nodes of the chip package model. A reduced node resistor model and a reduced node inductor model are created using the inductance and the resistance of the chip package model. A combined reduced node resistor-inductor chip package model is formed by combining the reduced node resistor model and reduced node inductor model.

摘要翻译： 提供计算机实现的方法，数据处理系统和计算机可用程序代码以减少芯片封装模型。 响应于接收芯片封装模型，测量芯片封装模型的电感和电阻。 电感和电阻仅使用芯片封装模型的一组外部节点进行测量。 使用芯片封装模型的电感和电阻来创建减少节点电阻器模型和降低节点电感器模型。 通过组合减少节点电阻器模型和减少节点电感器模型形成组合的减少节点电阻器 - 电感器芯片封装模型。