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公开(公告)号：US20080294296A1
公开(公告)日：2008-11-27
申请号：US11805581
申请日：2007-05-23
IPC分类号： G05D23/00
CPC分类号： G05D23/1917 , G06F1/206
摘要： Embodiments of the present invention are directed to systems and methods for controlling the temperature of an internal device while reducing or minimizing the involvement of the host. Thus, some of the heat monitoring and remediation work may be offloaded to the actual device itself. The device may monitor its own temperature and, in the event of high temperature, perform device specific heat reduction actions without involving the host. Furthermore, the device may, upon detecting temperature within a predefined range, alert the host of a high temperature condition in order to allow the host to perform temperature reduction measures. Also, the device may, upon detecting temperature within a predefined range, alert the host of an impending device shutdown and shut the device down. In addition, the device may periodically save its temperature into non-volatile memory in order to create a temperature log.
摘要翻译： 本发明的实施例涉及用于在减少或最小化宿主参与的同时控制内部装置的温度的系统和方法。 因此，一些热监测和修复工作可能被卸载到实际设备本身。 该设备可以监控其自身的温度，并且在高温的情况下，可以在不涉及主机的情况下执行设备特定的减热动作。 此外，在检测到预定范围内的温度时，该装置可以向主机报警高温状态，以允许主机执行降温措施。 而且，当检测到预定范围内的温度时，设备可以警告主机即将关闭设备并关闭设备。 此外，设备可以周期性地将其温度保存到非易失性存储器中，以便创建温度记录。
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公开(公告)号：US07937188B2
公开(公告)日：2011-05-03
申请号：US11805581
申请日：2007-05-23
IPC分类号： G06F15/00
CPC分类号： G05D23/1917 , G06F1/206
摘要： Embodiments of the present invention are directed to systems and methods for controlling the temperature of an internal device while reducing or minimizing the involvement of the host. Thus, some of the heat monitoring and remediation work may be offloaded to the actual device itself. The device may monitor its own temperature and, in the event of high temperature, perform device specific heat reduction actions without involving the host. Furthermore, the device may, upon detecting temperature within a predefined range, alert the host of a high temperature condition in order to allow the host to perform temperature reduction measures. Also, the device may, upon detecting temperature within a predefined range, alert the host of an impending device shutdown and shut the device down. In addition, the device may periodically save its temperature into non-volatile memory in order to create a temperature log.
摘要翻译： 本发明的实施例涉及用于在减少或最小化宿主参与的同时控制内部装置的温度的系统和方法。 因此，一些热监测和修复工作可能被卸载到实际设备本身。 该设备可以监控其自身的温度，并且在高温的情况下，可以在不涉及主机的情况下执行设备特定的减热动作。 此外，在检测到预定范围内的温度时，该装置可以向主机报警高温状态，以允许主机执行降温措施。 而且，当检测到预定范围内的温度时，设备可以警告主机即将关闭设备并关闭设备。 此外，设备可以周期性地将其温度保存到非易失性存储器中，以便创建温度记录。
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公开(公告)号：US08631169B2
公开(公告)日：2014-01-14
申请号：US12134985
申请日：2008-06-06
IPC分类号： G06F13/28
CPC分类号： G06F13/28 , G06F13/382
摘要： Restoring retired transaction identifiers (TID) associated with Direct Memory Access (DMA) commands without waiting for all DMA traffic to terminate is disclosed. A scoreboard is used to track retired TIDs and selectively restore retired TIDs on the fly. DMA engines fetch a TID, and use it to tag every DMA request. If the request is completed, the TID can be recycled to be used to tag a subsequent request. However, if a request is not completed, the TID is retired. Retired TIDs can be restored without having to wait for DMA traffic to end. Any retired TID value may be mapped to a bit location inside a scoreboard. All processors in the system may have access to read and clear the scoreboard. Clearing the TID scoreboard may trigger a DMA engine to restore the TID mapped to that location, and the TID may be used again.
摘要翻译： 公开了恢复与直接存储器访问（DMA）命令相关联的退出事务标识符（TID），而不等待所有DMA流量终止。 记分牌用于跟踪退休的TID，并有选择地恢复退休的TID。 DMA引擎获取TID，并使用它来标记每个DMA请求。 如果请求完成，则可以回收TID以用于标记后续请求。 但是，如果请求未完成，则TID已退休。 可以恢复退出的TID，而不必等待DMA流量结束。 任何退休的TID值都可以映射到记分板内的位置。 系统中的所有处理器都可以访问读取和清除记分板。 清除TID记分板可能会触发DMA引擎恢复映射到该位置的TID，并且可以再次使用TID。
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公开(公告)号：US20090307386A1
公开(公告)日：2009-12-10
申请号：US12134985
申请日：2008-06-06
IPC分类号： G06F13/28
CPC分类号： G06F13/28 , G06F13/382
摘要： Restoring retired transaction identifiers (TID) associated with Direct Memory Access (DMA) commands without waiting for all DMA traffic to terminate is disclosed. A scoreboard is used to track retired TIDs and selectively restore retired TIDs on the fly. DMA engines fetch a TID, and use it to tag every DMA request. If the request is completed, the TID can be recycled to be used to tag a subsequent request. However, if a request is not completed, the TID is retired. Retired TIDs can be restored without having to wait for DMA traffic to end. Any retired TID value may be mapped to a bit location inside a scoreboard. All processors in the system may have access to read and clear the scoreboard. Clearing the TID scoreboard may trigger a DMA engine to restore the TID mapped to that location, and the TID may be used again.
摘要翻译： 公开了恢复与直接存储器访问（DMA）命令相关联的退出事务标识符（TID），而不等待所有DMA流量终止。 记分牌用于跟踪退休的TID，并有选择地恢复退休的TID。 DMA引擎获取TID，并使用它来标记每个DMA请求。 如果请求完成，则可以回收TID以用于标记后续请求。 但是，如果请求未完成，则TID已退休。 可以恢复退出的TID，而不必等待DMA流量结束。 任何退休的TID值都可以映射到记分板内的位置。 系统中的所有处理器都可以访问读取和清除记分板。 清除TID记分板可能会触发DMA引擎恢复映射到该位置的TID，并且可以再次使用TID。
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5.发明授权Efficient processing of groups of host access requests that may include zero length requests 有权高效处理可能包括零长度请求的主机访问请求组公开(公告)号：US07853735B2
公开(公告)日：2010-12-14
申请号：US11956262
申请日：2007-12-13
IPC分类号： G06F5/00
CPC分类号： G06F13/128
摘要： This is directed to methods and systems for handling access requests from a device to a host. The device may be a device that is part of the host, such as an HBA, an NIC, etc. The device may include a processor which runs firmware and which may generate various host access requests. The host access requests may be, for example, memory access requests, or DMA requests. The device may include a module for executing the host access requests, such as a data transfer block (DXB). The DXB may process incoming host access requests and return notifications of completion to the processor. For various reasons, the processor may from time to time issue null or zero length requests. Embodiments of the present invention ensure that the notifications of completion for all requests, including the zero length requests, are sent to the processor in the same order as the requests.
摘要翻译： 这涉及用于处理从设备到主机的访问请求的方法和系统。 设备可以是作为主机的一部分的设备，诸如HBA，NIC等。设备可以包括运行固件并且可以生成各种主机访问请求的处理器。 主机访问请求可以是例如存储器访问请求或DMA请求。 该设备可以包括用于执行主机访问请求的模块，例如数据传输块（DXB）。 DXB可以处理传入的主机访问请求并将完成的通知返回给处理器。 由于各种原因，处理器可能不时地发出空或零长度的请求。 本发明的实施例确保包括零长度请求的所有请求的完成通知以与请求相同的顺序被发送到处理器。
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公开(公告)号：US08111696B2
公开(公告)日：2012-02-07
申请号：US12251290
申请日：2008-10-14
IPC分类号： H04L12/28
CPC分类号： H04L67/1097 , H04L43/0811 , H04L69/324
摘要： A method is disclosed for indicating a status of a transfer of data from a first device to a second device over a network. In one embodiment, the data includes one or more data frames. Each frame includes a header having one or more bits. The method includes setting a last bit of the one or more bits in the header of a last frame of the one or more data frames to a first value if the status of the transfer of data is good and setting the value of the last bit of the last data frame to a second value if the transfer of data failed. This results in a less congested, more efficient network.
摘要翻译： 公开了一种用于指示通过网络将数据从第一设备传送到第二设备的状态的方法。 在一个实施例中，数据包括一个或多个数据帧。 每个帧包括具有一个或多个比特的报头。 该方法包括：如果数据传输状态良好并且将最后一位的值设置为最大位，则将一个或多个数据帧的最后一帧的报头中的一个或多个位的最后位设置为第一值 如果数据传输失败，则最后一个数据帧为第二个值。 这导致网络拥塞较少，网络效率更高。
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7.发明申请EFFICIENT PROCESSING OF GROUPS OF HOST ACCESS REQUESTS THAT MAY INCLUDE ZERO LENGTH REQUESTS 有权可能包含零长度要求的主机访问权限组的有效处理公开(公告)号：US20090157918A1
公开(公告)日：2009-06-18
申请号：US11956262
申请日：2007-12-13
IPC分类号： G06F13/14
CPC分类号： G06F13/128
摘要： This is directed to methods and systems for handling access requests from a device to a host. The device may be a device that is part of the host, such as an HBA, an NIC, etc. The device may include a processor which runs firmware and which may generate various host access requests. The host access requests may be, for example, memory access requests, or DMA requests. The device may include a module for executing the host access requests, such as a data transfer block (DXB). The DXB may process incoming host access requests and return notifications of completion to the processor. For various reasons, the processor may from time to time issue null or zero length requests. Embodiments of the present invention ensure that the notifications of completion for all requests, including the zero length requests, are sent to the processor in the same order as the requests.
摘要翻译： 这涉及用于处理从设备到主机的访问请求的方法和系统。 设备可以是作为主机的一部分的设备，诸如HBA，NIC等。设备可以包括运行固件并且可以生成各种主机访问请求的处理器。 主机访问请求可以是例如存储器访问请求或DMA请求。 该设备可以包括用于执行主机访问请求的模块，例如数据传输块（DXB）。 DXB可以处理传入的主机访问请求并将完成的通知返回给处理器。 由于各种原因，处理器可能不时地发出空或零长度的请求。 本发明的实施例确保包括零长度请求的所有请求的完成通知以与请求相同的顺序被发送到处理器。
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公开(公告)号：US20090172287A1
公开(公告)日：2009-07-02
申请号：US11966900
申请日：2007-12-28
IPC分类号： G06F12/08
CPC分类号： G06F12/0888 , G06F12/0835 , G06F12/0893 , G06F2212/1024 , G06F2212/1044 , G06F2212/604 , G06F2212/6046 , G06F2212/608 , G06F2212/621
摘要： Embodiments of the current invention permit a user to allocate cache memory to main memory more efficiently. The processor or a user allocates the cache memory and associates the cache memory to the main memory location, but suppresses or bypassing reading the main memory data into the cache memory. Some embodiments of the present invention permit the user to specify how many cache lines are allocated at a given time. Further, embodiments of the present invention may initialize the cache memory to a specified pattern. The cache memory may be zeroed or set to some desired pattern, such as all ones. Alternatively, a user may determine the initialization pattern through the processor.
摘要翻译： 本发明的实施例允许用户更有效地向主存储器分配高速缓冲存储器。 处理器或用户分配高速缓冲存储器并将缓存存储器与主存储器位置相关联，但是抑制或绕过将主存储器数据读取到高速缓冲存储器中。 本发明的一些实施例允许用户指定在给定时间分配多少高速缓存行。 此外，本发明的实施例可以将高速缓存存储器初始化为指定的模式。 高速缓冲存储器可以被归零或设置为某些期望的模式，例如所有模式。 或者，用户可以通过处理器确定初始化模式。
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公开(公告)号：US08892823B2
公开(公告)日：2014-11-18
申请号：US11966900
申请日：2007-12-28
CPC分类号： G06F12/0888 , G06F12/0835 , G06F12/0893 , G06F2212/1024 , G06F2212/1044 , G06F2212/604 , G06F2212/6046 , G06F2212/608 , G06F2212/621
摘要： Embodiments of the current invention permit a user to allocate cache memory to main memory more efficiently. The processor or a user allocates the cache memory and associates the cache memory to the main memory location, but suppresses or bypassing reading the main memory data into the cache memory. Some embodiments of the present invention permit the user to specify how many cache lines are allocated at a given time. Further, embodiments of the present invention may initialize the cache memory to a specified pattern. The cache memory may be zeroed or set to some desired pattern, such as all ones. Alternatively, a user may determine the initialization pattern through the processor.
摘要翻译： 本发明的实施例允许用户更有效地向主存储器分配高速缓冲存储器。 处理器或用户分配高速缓冲存储器并将缓存存储器与主存储器位置相关联，但是抑制或绕过将主存储器数据读取到高速缓冲存储器中。 本发明的一些实施例允许用户指定在给定时间分配多少高速缓存行。 此外，本发明的实施例可以将高速缓存存储器初始化为指定的模式。 高速缓冲存储器可以被归零或设置为某些期望的模式，例如所有模式。 或者，用户可以通过处理器确定初始化模式。
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