公开(公告)号：US20120283981A1

公开(公告)日：2012-11-08

申请号：US13550008

申请日：2012-07-16

申请人： Michiko INOUE ,  Tomokazu YONEDA ,  Yasuo SATO

发明人： Michiko INOUE ,  Tomokazu YONEDA ,  Yasuo SATO

IPC分类号： G01R31/26

CPC分类号： G01R31/318371 ,  G01R31/31721 ,  G01R31/318385 ,  G01R31/318544

摘要： A test pattern is sequentially selected from an original test pattern sequence constituted by a plurality of test patterns including a don't care bit. Power consumption in each of regions obtained by substantially equally dividing a layout region of a semiconductor integrated circuit in a case where a don't care value is specified in the selected test pattern and this selected test pattern is applied to the semiconductor integrated circuit is estimated. A searching is conducted for a don't care value of the selected test pattern which minimizes a variation in power consumption among the regions by repeatedly changing the don't care value and repeatedly estimating power consumption in the regions. A new test pattern sequence constituted by a plurality of test patterns including no don't care bit is generated by defining the don't care value obtained by the searching as a don't care value of the selected test pattern.

摘要翻译： 从由包括无关位的多个测试图案构成的原始测试图案序列中顺序地选择测试图案。 估计在所选择的测试图形中指定了不关心值的情况下基本上等分半导体集成电路的布局区域获得的每个区域中的功耗，并将该选择的测试图案应用于半导体集成电路 。 对所选择的测试图案进行搜索，通过重复地改变不关心值并重复地估计区域中的功耗，从而最小化区域之间的功耗变化。 通过将通过搜索获得的无关心值定义为所选择的测试图案的无关价值，生成由包括不关心位的多个测试图案构成的新测试图案序列。