公开(公告)号：US20210055963A1

公开(公告)日：2021-02-25

申请号：US16591294

申请日：2019-10-02

Applicant: Microchip Technology Incorporated

Inventor： Hongming An ,  John Junling Zang ,  Henry Liang ,  Thor Xia ,  Congqing Xiong

IPC: G06F9/50 ,  G06F1/324 ,  H04L12/40 ,  G06F1/3209 ,  H04L12/10

Abstract: Circuitry for detecting valid signals on a single pair Ethernet bus and related systems are described. Also described are circuits and related systems for wake detection at a physical layer of a network segment, and in some embodiments, wake detection circuitry may include, or use, the signal detection circuitry. In some cases, a low frequency clock generator may be used to clock wake detection circuitry, including during low power modes of operation. In some cases, the low frequency clock generator may be enabled or disabled, selectively, to limit power consumption.

公开(公告)号：US10440160B2

公开(公告)日：2019-10-08

申请号：US16007176

申请日：2018-06-13

Applicant: Microchip Technology Incorporated

Inventor： Jiachi Yu ,  Dixon Chen ,  Hongming An ,  John Zang ,  Kevin Yang

IPC: H04L29/08

Abstract: An apparatus includes an encoder circuit and a scrambler circuit configured to receive a frame, the frame including a preamble and a payload. The scrambler circuit is further configured to scramble contents of the frame including the payload and at least a portion of the preamble, provide synchronization information with results of scrambling the contents, and send results of scrambling the contents to the encoder circuit.

公开(公告)号：US20250013287A1

公开(公告)日：2025-01-09

申请号：US18766265

申请日：2024-07-08

Applicant: Microchip Technology Incorporated

Inventor： Venkatraman Iyer ,  Hussein El-Shafie ,  Hongming An

IPC: G06F1/3296 ,  G06F1/3206

Abstract: A method includes providing a system basis chip that supports at least two power states: a sleep state and an awake state; monitoring for power state information via a hardware interface and via a communication interface, wherein the hardware interface allows communication between a physical layer (PHY) transceiver implemented at the system basis chip and a PHY controller implemented at a microcontroller, and wherein the communication interface allows communication between the system basis chip and the microcontroller; and coordinating a change in power state of the system basis chip at least partially based on reception of power state information via the hardware interface and the communication interface.

公开(公告)号：US20240195396A1

公开(公告)日：2024-06-13

申请号：US18531232

申请日：2023-12-06

Applicant: Microchip Technology Incorporated

Inventor： Jiachi Yu ,  Henry Liang ,  James Ho ,  Galin I. Ivanov ,  Kevin Yang ,  Dixon Chen ,  Congqing Xiong ,  Hongming An

IPC: H03K5/1252 ,  H03K19/20

CPC classification number: H03K5/1252 ,  H03K19/20 ,  H03K2005/00019

Abstract: Reducing emissions of predetermined frequencies using delay elements and related apparatuses, methods, and systems are disclosed. An apparatus includes an input terminal to receive a signal, delay elements electrically connected to the input terminal, an output terminal to provide a reduced slew rate signal, and combination circuitry electrically connected to the delay elements and the output terminal. The delay elements provide delayed signals responsive to the received signal. Respective ones of the delayed signals include delayed versions of the received signal. The combination circuitry combines the delayed signals to generate the reduced slew rate signal. Delays associated with the delay elements are chosen to reduce emissions of one or more predetermined frequencies of the reduced slew rate signal as compared to the received signal.

公开(公告)号：US11121782B2

公开(公告)日：2021-09-14

申请号：US16588714

申请日：2019-09-30

Applicant: Microchip Technology Incorporated

Inventor： John Junling Zang ,  Dixon Chen ,  Hongming An ,  Jiachi Yu ,  Kevin Yang ,  Yanzi Xu ,  Henry Liang

IPC: H04B17/17 ,  H04B17/29 ,  H04L29/08 ,  H04L12/40

Abstract: Various embodiments relate to detecting a cable fault within a 10SPE network. A method may include transmitting a pulse signal to a cable of a shared bus from a node, and observing a signal received at the node in response to the pulse signal. The method may also include determining a fault condition of the cable based on the pulse signal and on an amplitude of each sample of a number of samples of the one or more observed signals.

公开(公告)号：US20250007515A1

公开(公告)日：2025-01-02

申请号：US18759523

申请日：2024-06-28

Applicant: Microchip Technology Incorporated

Inventor： Lars Beilschmidt ,  Venkatraman lyer ,  Hongming An ,  Shivanand I. Akkihal

IPC: H03K19/003 ,  H03K19/00 ,  H03K19/0175

Abstract: An apparatus may include a voltage source, a voltage protection circuit, and a chip powered at least in part via the voltage protection circuit. The chip may include at least one regulated voltage source; and a logic circuit. The logic circuit may determine a state of a supply voltage produced by the voltage protection circuit; determine a state of an input voltage produced by the voltage source; and determine and indicate a predicted state of the supply voltage produced by the voltage protection circuit or a predicted state of the at least one regulated voltage source, in either case at least partially based on the determined state of the supply voltage produced by the voltage protection circuit and the determined state of the input voltage produced by the voltage source.

公开(公告)号：US20240388416A1

公开(公告)日：2024-11-21

申请号：US18667841

申请日：2024-05-17

Applicant: Microchip Technology Incorporated

Inventor： Jiachi Yu ,  Dixon Chen ,  Thor Lei Xia ,  Kevin Yang ,  Hongming An ,  Markus N. Becht

IPC: H04L7/04 ,  G06F18/30

Abstract: One or more examples relate to a method that includes: applying oversampling to data on a reception datapath of a physical layer; generating a first signal indicating relationships between patterns exhibited by portions of oversampled data and a predetermined pattern; generating a second signal indicating an observed feature of the first signal, the observed feature indicative of a highest relationship between the patterns exhibited by respective portions of oversampled data and the predetermined pattern; and providing the second signal to indicate presence of a portion of data corresponding to the predetermined pattern at a coupled portion of the reception datapath of the physical layer.

公开(公告)号：US20230268891A1

公开(公告)日：2023-08-24

申请号：US17664086

申请日：2022-05-19

Applicant: Microchip Technology Incorporated

Inventor： Henry Liang ,  Hongming An ,  James Ho ,  Congqing Xiong

IPC: H03F1/56 ,  H03F1/52

CPC classification number: H03F1/56 ,  H03F1/523 ,  H03F2200/264 ,  H03F2200/426

Abstract: This description relates, generally, to protecting a circuit from an input voltage. Various examples include an apparatus including one or more circuits to draw current from, or provide current to, a pair of connectors for an input circuit. The connectors may be for electrical coupling to first and second terminals of a twisted pair. The one or more circuits may be at least partially responsive to positive and negative biasing signals. The apparatus may additionally include an operational amplifier to generate the positive and negative biasing signals. The operational amplifier may include: a first input terminal at least partially responsive to a reference voltage and a second input terminal at least partially responsive to a common-mode voltage of the input circuit. Related systems and methods are also disclosed.

公开(公告)号：US11074209B2

公开(公告)日：2021-07-27

申请号：US16588562

申请日：2019-09-30

Applicant: Microchip Technology Incorporated

Inventor： Hongming An ,  James Ho ,  Congqing Xiong ,  Henry Liang ,  John Junling Zang

IPC: G06F13/40 ,  G06F1/10 ,  G06F9/4401 ,  G06F9/30

Abstract: Circuitry of a physical layer for interfacing with a communication bus of a wired local area network is disclosed. The circuitry includes a variable delay driver operably coupled to a communication bus. The communication bus includes a shared transmission medium. The variable delay driver is configured to control a slew rate of a driven transmit signal at the driver output. The circuitry also includes receiver circuitry operably coupled to the communication bus. The circuitry further includes a common mode dimmer operably coupled to the receiver circuitry and the communication bus. The common mode dimmer is configured to protect the receiver circuitry from common mode interference.

公开(公告)号：US20190268452A1

公开(公告)日：2019-08-29

申请号：US16007119

申请日：2018-06-13

Applicant: Microchip Technology Incorporated

Inventor： Jiachi Yu ,  Dixon Chen ,  Hongming An ,  John Zang ,  Kevin Yang

IPC: H04L29/08

Abstract: An apparatus includes an encoder circuit and a scrambler circuit configured to receive a frame, the frame including a preamble and a payload. The scrambler circuit is further configured to scramble contents of the frame including the payload and at least a portion of the preamble, provide synchronization information with results of scrambling the contents, and send results of scrambling the contents to the encoder circuit.