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公开(公告)号：US09858083B2
公开(公告)日：2018-01-02
申请号：US14204208
申请日：2014-03-11
Applicant: Microchip Technology Incorporated
Inventor： Michael I. Catherwood , Brant Ivey , Igor Wojewoda , David Mickey , Joseph Kanellopoulos
CPC classification number: G06F9/4401 , G06F8/656 , G06F9/441
Abstract: A central processing unit with dual boot capabilities is disclosed comprising an instruction memory further comprising a first and second memory area which are configured to be individually programmable, wherein first and second memory area can be assigned to an active memory from which instructions are executed and an inactive memory, respectively. The instruction set for the central processing unit comprises a dedicated instruction that allows to perform a swap from the an active memory area to an inactive memory area, wherein the swap is performed by executing the dedicated instruction in the active memory followed by a program flow change instruction in the active memory, whereupon the inactive memory becomes the new active memory and the active memory becomes the new inactive memory and execution of instructions continues in the new active memory.
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公开(公告)号：US09619231B2
公开(公告)日：2017-04-11
申请号：US14200417
申请日：2014-03-07
Applicant: Microchip Technology Incorporated
Inventor： Michael I. Catherwood , Bryan Kris , David Mickey , Joseph Kanellopoulos
CPC classification number: G06F9/30145 , G06F9/3009 , G06F9/3865 , G06F9/462
Abstract: A central processing unit (CPU) having an interrupt unit for interrupting execution of instructions, a plurality context defining register sets, wherein each set of registers having the same number of CPU registers, a switching unit for coupling a selected register set within the CPU, wherein the switching unit switches to a predetermined register set of the plurality of context defining register sets upon occurrence of an exception, and a control register configured to control selection of a register set of the plurality of context defining register initiated by an instruction and further operable to indicate a currently used context.
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公开(公告)号：US20150019847A1
公开(公告)日：2015-01-15
申请号：US14200417
申请日：2014-03-07
Applicant: Microchip Technology Incorporated
Inventor： Michael I. Catherwood , Bryan Kris , David Mickey , Joseph Kanellopoulos
CPC classification number: G06F9/30145 , G06F9/3009 , G06F9/3865 , G06F9/462
Abstract: A central processing unit (CPU) having an interrupt unit for interrupting execution of instructions, a plurality context defining register sets, wherein each set of registers having the same number of CPU registers, a switching unit for coupling a selected register set within the CPU, wherein the switching unit switches to a predetermined register set of the plurality of context defining register sets upon occurrence of an exception, and a control register configured to control selection of a register set of the plurality of context defining register initiated by an instruction and further operable to indicate a currently used context.
Abstract translation: 具有用于中断执行指令的中断单元的中央处理单元（CPU），多个上下文定义寄存器组，其中每组具有相同数目的CPU寄存器的寄存器，用于耦合所选择的CPU内的寄存器组的切换单元， 其中所述切换单元在出现异常时切换到所述多个上下文定义寄存器组的预定寄存器组，以及控制寄存器，其被配置为控制由指令启动的所述多个上下文定义寄存器的寄存器组的选择，并且还可操作 以指示当前使用的上下文。
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公开(公告)号：US20140281465A1
公开(公告)日：2014-09-18
申请号：US14204208
申请日：2014-03-11
Applicant: Microchip Technology Incorporated
Inventor： Michael I. Catherwood , Brant Ivey , Igor Wojewoda , David Mickey , Joseph Kanellopoulos
IPC: G06F9/44
CPC classification number: G06F9/4401 , G06F8/656 , G06F9/441
Abstract: A central processing unit with dual boot capabilities is disclosed comprising an instruction memory further comprising a first and second memory area which are configured to be individually programmable, wherein first and second memory area can be assigned to an active memory from which instructions are executed and an inactive memory, respectively. The instruction set for the central processing unit comprises a dedicated instruction that allows to perform a swap from the an active memory area to an inactive memory area, wherein the swap is performed by executing the dedicated instruction in the active memory followed by a program flow change instruction in the active memory, whereupon the inactive memory becomes the new active memory and the active memory becomes the new inactive memory and execution of instructions continues in the new active memory.
Abstract translation: 公开了一种具有双引导功能的中央处理单元，包括指令存储器，进一步包括被配置为可单独编程的第一和第二存储器区域，其中第一和第二存储器区域可被分配给执行指令的有效存储器， 不活动内存。 用于中央处理单元的指令集包括允许执行从活动存储器区域到非活动存储器区域的交换的专用指令，其中通过在活动存储器中执行专用指令执行交换，随后进行程序流程改变 指令在活动存储器中，因此非活动存储器变为新的活动存储器，并且活动存储器变为新的非活动存储器，并且新的活动存储器中的指令的执行继续。
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