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公开(公告)号：US09858083B2
公开(公告)日：2018-01-02
申请号：US14204208
申请日：2014-03-11
Applicant: Microchip Technology Incorporated
Inventor： Michael I. Catherwood , Brant Ivey , Igor Wojewoda , David Mickey , Joseph Kanellopoulos
CPC classification number: G06F9/4401 , G06F8/656 , G06F9/441
Abstract: A central processing unit with dual boot capabilities is disclosed comprising an instruction memory further comprising a first and second memory area which are configured to be individually programmable, wherein first and second memory area can be assigned to an active memory from which instructions are executed and an inactive memory, respectively. The instruction set for the central processing unit comprises a dedicated instruction that allows to perform a swap from the an active memory area to an inactive memory area, wherein the swap is performed by executing the dedicated instruction in the active memory followed by a program flow change instruction in the active memory, whereupon the inactive memory becomes the new active memory and the active memory becomes the new inactive memory and execution of instructions continues in the new active memory.
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公开(公告)号：US12093688B2
公开(公告)日：2024-09-17
申请号：US17989067
申请日：2022-11-17
Applicant: Microchip Technology Incorporated
Inventor： Michael Catherwood , David Mickey , Ashish Desai , Jason Sachs , Calum Wilkie
IPC: G06F9/30
CPC classification number: G06F9/30032 , G06F9/30123
Abstract: An article of manufacture includes a non-transitory machine-readable medium. The medium includes instructions that cause a processor to execute a shift instruction. The shift instruction is to cause a source data in memory to be shifted left or shifted right. The shift instruction is to include a source parameter and a bit size parameter. The processor is to execute the shift instruction through a shift of a first source word of the source data by the bit size parameter to yield a first intermediate word, a shift of a second source word of the source data by the bit size parameter to yield a second intermediate word and a first set of shifted-out bits, and through execution of a logical OR operation on the first intermediate word and the first set of shifted-out bits to yield a first result word.
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公开(公告)号：US20230176898A1
公开(公告)日：2023-06-08
申请号：US18073075
申请日：2022-12-01
Applicant: Microchip Technology Incorporated
Inventor： Michael Catherwood , Howard Schlunder , David Mickey
CPC classification number: G06F9/4831 , G06F8/71
Abstract: A system includes non-transitory computer readable memory and a processor. The non-transitory computer readable memory stores a current processor interrupt priority level and a current disable interrupt control (DISICTL) interrupt priority level. The processor to update the current processor interrupt priority level based on respective interrupt priority levels associated with respective exceptions, and update the current DISICTL interrupt priority level based on a respective DISICTL instruction, wherein the respective DISICTL instruction specifies a respective user-definable DISICTL interrupt priority level. The processor determines a highest interrupt priority level between the current processor interrupt priority level and the current DISICTL interrupt priority level, and apply the highest interrupt priority level during execution of respective code.
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公开(公告)号：US20230176867A1
公开(公告)日：2023-06-08
申请号：US17989067
申请日：2022-11-17
Applicant: Microchip Technology Incorporated
Inventor： Michael Catherwood , David Mickey , Ashish Desai , Jason Sachs , Calum Wilkie
IPC: G06F9/30
CPC classification number: G06F9/30032
Abstract: An article of manufacture includes a non-transitory machine-readable medium. The medium includes instructions that cause a processor to execute a shift instruction. The shift instruction is to cause a source data in memory to be shifted left or shifted right. The shift instruction is to include a source parameter and a bit size parameter. The processor is to execute the shift instruction through a shift of a first source word of the source data by the bit size parameter to yield a first intermediate word, a shift of a second source word of the source data by the bit size parameter to yield a second intermediate word and a first set of shifted-out bits, and through execution of a logical OR operation on the first intermediate word and the first set of shifted-out bits to yield a first result word.
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公开(公告)号：US10802866B2
公开(公告)日：2020-10-13
申请号：US15141817
申请日：2016-04-28
Applicant: Microchip Technology Incorporated
Inventor： Michael Catherwood , David Mickey
IPC: G06F9/46 , G06F9/30 , G06F9/4401
Abstract: An integrated circuit device has a first central processing unit including a digital signal processing (DSP) engine, and a plurality of contexts, each context having a CPU context with a plurality of registers and a DSP context, wherein the DSP context has control bits and a plurality of DSP registers, wherein after a reset of the integrated circuit device the control bits of all DSP context are linked together such that data written to the control bits of a DSP context is written to respective control bits of all other DSP contexts and only after a context switch to another context and a modification of at least one of the control bits of the another DSP context, the control bits of the another context is severed from the link to form independent control bits of the DSP context.
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Patent Agency Ranking
公开(公告)号：US20230176866A1
公开(公告)日：2023-06-08
申请号：US17982980
申请日：2022-11-08
Applicant: Microchip Technology Incorporated
Inventor： Michael Catherwood , David Mickey , Ashish Desai , Jason Sachs , Calum Wilkie
IPC: G06F9/30
CPC classification number: G06F9/30032 , G06F9/30123
Abstract: An article of manufacture includes a non-transitory machine-readable medium. The medium includes instructions that cause a processor to execute a shift instruction. The shift instruction is to cause a source data in memory to be shifted left or shifted right. The shift instruction is to include a source parameter and a bit size parameter. The processor is to execute the shift instruction through a shift of a first source word of the source data by the bit size parameter to yield a first intermediate word, a shift of a second source word of the source data by the bit size parameter to yield a second intermediate word and a first set of shifted-out bits, and through execution of a logical OR operation on the first intermediate word and the first set of shifted-out bits to yield a first result word.
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公开(公告)号：US10120815B2
公开(公告)日：2018-11-06
申请号：US15184789
申请日：2016-06-16
Applicant: Microchip Technology Incorporated
Inventor： Michael Catherwood , David Mickey , Bryan Kris
Abstract: A single chip microcontroller has a master core and at least one slave core. The master core is clocked by a master system clock and the slave core is clocked by a slave system clock and wherein each core is associated with a plurality of peripheral devices to form a master microcontroller and a slave microcontroller, respectively. A communication interface is provided between the master microcontroller and the slave microcontroller, wherein the communication interface has a plurality of configurable directional data registers coupled with a flow control logic which is configurable to assign a direction to each of the plurality of configurable data registers.
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公开(公告)号：US09619231B2
公开(公告)日：2017-04-11
申请号：US14200417
申请日：2014-03-07
Applicant: Microchip Technology Incorporated
Inventor： Michael I. Catherwood , Bryan Kris , David Mickey , Joseph Kanellopoulos
CPC classification number: G06F9/30145 , G06F9/3009 , G06F9/3865 , G06F9/462
Abstract: A central processing unit (CPU) having an interrupt unit for interrupting execution of instructions, a plurality context defining register sets, wherein each set of registers having the same number of CPU registers, a switching unit for coupling a selected register set within the CPU, wherein the switching unit switches to a predetermined register set of the plurality of context defining register sets upon occurrence of an exception, and a control register configured to control selection of a register set of the plurality of context defining register initiated by an instruction and further operable to indicate a currently used context.
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公开(公告)号：US20150019847A1
公开(公告)日：2015-01-15
申请号：US14200417
申请日：2014-03-07
Applicant: Microchip Technology Incorporated
Inventor： Michael I. Catherwood , Bryan Kris , David Mickey , Joseph Kanellopoulos
CPC classification number: G06F9/30145 , G06F9/3009 , G06F9/3865 , G06F9/462
Abstract: A central processing unit (CPU) having an interrupt unit for interrupting execution of instructions, a plurality context defining register sets, wherein each set of registers having the same number of CPU registers, a switching unit for coupling a selected register set within the CPU, wherein the switching unit switches to a predetermined register set of the plurality of context defining register sets upon occurrence of an exception, and a control register configured to control selection of a register set of the plurality of context defining register initiated by an instruction and further operable to indicate a currently used context.
Abstract translation: 具有用于中断执行指令的中断单元的中央处理单元（CPU），多个上下文定义寄存器组，其中每组具有相同数目的CPU寄存器的寄存器，用于耦合所选择的CPU内的寄存器组的切换单元， 其中所述切换单元在出现异常时切换到所述多个上下文定义寄存器组的预定寄存器组，以及控制寄存器，其被配置为控制由指令启动的所述多个上下文定义寄存器的寄存器组的选择，并且还可操作 以指示当前使用的上下文。
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公开(公告)号：US20140281465A1
公开(公告)日：2014-09-18
申请号：US14204208
申请日：2014-03-11
Applicant: Microchip Technology Incorporated
Inventor： Michael I. Catherwood , Brant Ivey , Igor Wojewoda , David Mickey , Joseph Kanellopoulos
IPC: G06F9/44
CPC classification number: G06F9/4401 , G06F8/656 , G06F9/441
Abstract: A central processing unit with dual boot capabilities is disclosed comprising an instruction memory further comprising a first and second memory area which are configured to be individually programmable, wherein first and second memory area can be assigned to an active memory from which instructions are executed and an inactive memory, respectively. The instruction set for the central processing unit comprises a dedicated instruction that allows to perform a swap from the an active memory area to an inactive memory area, wherein the swap is performed by executing the dedicated instruction in the active memory followed by a program flow change instruction in the active memory, whereupon the inactive memory becomes the new active memory and the active memory becomes the new inactive memory and execution of instructions continues in the new active memory.
Abstract translation: 公开了一种具有双引导功能的中央处理单元，包括指令存储器，进一步包括被配置为可单独编程的第一和第二存储器区域，其中第一和第二存储器区域可被分配给执行指令的有效存储器， 不活动内存。 用于中央处理单元的指令集包括允许执行从活动存储器区域到非活动存储器区域的交换的专用指令，其中通过在活动存储器中执行专用指令执行交换，随后进行程序流程改变 指令在活动存储器中，因此非活动存储器变为新的活动存储器，并且活动存储器变为新的非活动存储器，并且新的活动存储器中的指令的执行继续。
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