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1.发明申请公开(公告)号：US20220095377A1
公开(公告)日：2022-03-24
申请号：US17457358
申请日：2021-12-02
IPC分类号： H04W74/08
摘要： Various embodiments relate to wired local area networks. A method may include detecting, at a node in a wired local area network, at least one event. A physical layer device of the network node is configured to implement a physical level collision avoidance (PLCA) sublayer. The at least one event may include at least one of an amount of data stored in a first-in-first-out (FIFO) buffer of the node being at least a threshold amount, and a received packet being a precision time protocol (PTP) packet incurring variable delay. The method may further include emulating a collision at the node in response to the at least one detected event.
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2.发明授权公开(公告)号：US11876616B2
公开(公告)日：2024-01-16
申请号：US17815521
申请日：2022-07-27
发明人： Michael Rentschler , Martin Miller , Thorben Link , Venkat Iyer
IPC分类号： H04L1/00 , H04L41/0816 , H04L41/12 , H04L67/104 , H04L67/1061 , H04L69/323
CPC分类号： H04L1/0002 , H04L41/0816 , H04L41/12 , H04L67/1048 , H04L67/1051 , H04L67/1063 , H04L69/323
摘要： Various examples relate to a wired local area network (WLAN) including a shared transmission medium. An apparatus includes a beacon counter and an operational mode controller. The beacon counter is operably coupled to a line of a shared transmission medium of a wired local area network. The beacon counter is to count beacon signals on the line and determine a beacon count over a predetermined time period, or a beacon rate of the beacon signals. The operational mode controller is to control the apparatus to take over operation as a master node of the wired local area network based, at least in part, on a maximum bus cycle length of bus cycles on the line and responsive to the beacon count or the beacon rate.
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3.发明申请公开(公告)号：US20220368451A1
公开(公告)日：2022-11-17
申请号：US17815521
申请日：2022-07-27
IPC分类号： H04L1/00 , H04L41/0816 , H04L41/12 , H04L67/104 , H04L67/1061 , H04L69/323
摘要： Various examples relate to a wired local area network (WLAN) including a shared transmission medium. An apparatus includes a beacon counter and an operational mode controller. The beacon counter is operably coupled to a line of a shared transmission medium of a wired local area network. The beacon counter is to count beacon signals on the line and determine a beacon count over a predetermined time period, or a beacon rate of the beacon signals. The operational mode controller is to control the apparatus to take over operation as a master node of the wired local area network based, at least in part, on a maximum bus cycle length of bus cycles on the line and responsive to the beacon count or the beacon rate.
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4.发明申请公开(公告)号：US20200351119A1
公开(公告)日：2020-11-05
申请号：US16674999
申请日：2019-11-05
发明人： Michael Rentschler , Venkat Iyer
IPC分类号： H04L12/40 , H04L12/815 , H04L12/403
摘要： Disclosed embodiments relate, generally, to traffic shaping at a network segment having a shared bus. Some embodiments relate to performing aspects of the traffic shaping at a physical layer device. In some cases, transmit timeslot signaling may be tuned at a physical layer device to create transmit timeslots that are aligned with the traffic shaping profile.
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公开(公告)号：US20220013149A1
公开(公告)日：2022-01-13
申请号：US17305561
申请日：2021-07-09
发明人： Michael Rentschler , Thorben Link
IPC分类号： G11B27/10 , H04N21/8547 , H04N21/81 , H03K19/20
摘要： Synchronization for audio systems and related systems and circuitry are disclosed. An audio system includes a word select line of a digital audio interface, a serial clock line of the digital audio interface, and hardware circuitry. The hardware circuitry is configured to provide a word select signal to the word select line and a serial clock signal to the serial clock line. The word select signal is configured to indicate channels of a serial data signal provided to a serial data line of the digital audio interface. The hardware circuitry is also configured to synchronize the serial clock signal to a clock reference stream of an audio stream communicated via a network interface.
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6.发明授权公开(公告)号：US11050501B2
公开(公告)日：2021-06-29
申请号：US16440775
申请日：2019-06-13
发明人： Michael Rentschler
摘要： A microcontroller includes a packet matching circuit, a hardware timer circuit, and a processor. The packet matching circuit is configured to match contents of received packets to the microcontroller and identify whether a packet has been received. The hardware timer circuit is configured to provide a synchronization timestamp based on a signal from the packet matching circuit that a synchronization packet has been matched, and provide a follow-up timestamp based on a signal from the packet matching circuit that a follow-up packet has been matched after reception of the synchronization packet. The processor is configured to adjust a clock base to determine a synchronized clock base based upon the synchronization timestamp and upon the follow-up timestamp.
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7.发明申请公开(公告)号：US20200343993A1
公开(公告)日：2020-10-29
申请号：US16749695
申请日：2020-01-22
发明人： Michael Rentschler , Martin Miller , Thorben Link , Venkat Iyer
摘要： Various embodiments relate to a wired local area network (WLAN) including a shared transmission medium (e.g., a 10SPE network). A method may include detecting an event in a WLAN including physical level collision avoidance (PLCA). The method may also include disabling a beacon of a first node operating as a master of the WLAN in response to the event. Further, the method may include enabling a second node to operate as the master of the WLAN.
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8.发明申请公开(公告)号：US20190386763A1
公开(公告)日：2019-12-19
申请号：US16440775
申请日：2019-06-13
发明人： Michael Rentschler
摘要： A microcontroller includes a packet matching circuit, a hardware timer circuit, and a processor. The packet matching circuit is configured to match contents of received packets to the microcontroller and identify whether a packet has been received. The hardware timer circuit is configured to provide a synchronization timestamp based on a signal from the packet matching circuit that a synchronization packet has been matched, and provide a follow-up timestamp based on a signal from the packet matching circuit that a follow-up packet has been matched after reception of the synchronization packet. The processor is configured to adjust a clock base to determine a synchronized clock base based upon the synchronization timestamp and upon the follow-up timestamp.
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公开(公告)号：US12062385B2
公开(公告)日：2024-08-13
申请号：US17305561
申请日：2021-07-09
发明人： Michael Rentschler , Thorben Link
CPC分类号： G11B27/10 , G06F1/04 , G06F1/12 , H03K19/20 , H04N21/8106 , H04N21/8547
摘要： Synchronization for audio systems and related systems and circuitry are disclosed. An audio system includes a word select line of a digital audio interface, a serial clock line of the digital audio interface, and hardware circuitry. The hardware circuitry is configured to provide a word select signal to the word select line and a serial clock signal to the serial clock line. The word select signal is configured to indicate channels of a serial data signal provided to a serial data line of the digital audio interface. The hardware circuitry is also configured to synchronize the serial clock signal to a clock reference stream of an audio stream communicated via a network interface.
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10.发明授权公开(公告)号：US11197322B2
公开(公告)日：2021-12-07
申请号：US16843648
申请日：2020-04-08
IPC分类号： H04W74/08
摘要： Various embodiments relate to wired local area networks. A method may include detecting, at a node in a wired local area network, at least one event. A physical layer device of the network node is configured to implement a physical level collision avoidance (PLCA) sublayer. The at least one event may include at least one of an amount of data stored in a first-in-first-out (FIFO) buffer of the node being at least a threshold amount, and a received packet being a precision time protocol (PTP) packet incurring variable delay. The method may further include emulating a collision at the node in response to the at least one detected event.
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