公开(公告)号：US11461139B2

公开(公告)日：2022-10-04

申请号：US16842870

申请日：2020-04-08

Applicant: Microchip Technology Incorporated

Inventor： Michael Simmons ,  Anjana Priya Sistla ,  Priyank Gupta

IPC: G06F9/50 ,  G06F8/41 ,  G06F9/54 ,  G06F12/02

Abstract: An apparatus includes processing cores, memory blocks, a connection between each of processing core and memory block, chip selection circuit, and chip selection circuit busses between the chip selection circuit and each of the memory blocks. Each memory block includes a data port and a memory check port. The chip selection circuit is configured to enable writing data from a highest priority core through respective data ports of the memory blocks. The chip selection circuit is further configured to enable writing data from other cores through respective memory check ports of the memory blocks.

公开(公告)号：US20200242055A1

公开(公告)日：2020-07-30

申请号：US16258171

申请日：2019-01-25

Applicant: Microchip Technology Incorporated

Inventor： Narendra Raj S V ,  Priyank Gupta ,  Michael Simmons

IPC: G06F13/16 ,  G06F5/06 ,  G06F3/06

Abstract: A buffer interface, data transport method, and computing system are described in which a buffer interface may be configured for communicating data samples to and from frame buffers defined in a memory. The configurable buffer interfaces and frame buffers provide a flexible and scalable platform for use with many applications.

公开(公告)号：US20220092006A1

公开(公告)日：2022-03-24

申请号：US17457185

申请日：2021-12-01

Applicant: Microchip Technology Incorporated

Inventor： Narendra Raj S V ,  Priyank Gupta ,  Michael Simmons

IPC: G06F13/16 ,  G06F3/06 ,  G06F5/06

Abstract: Disclosed examples include an apparatus. The apparatus may include first interfaces, second interfaces, a bus interface, and a buffer interface. The first interfaces may be to communicate at first data widths via first interconnects for operable coupling with data samples sources. The second interface may be to communicate at second data widths via second interconnects for operable coupling with data sinks. The buffer interface may be to communicate with a system to process data samples sampled using different sampling rates according to processing frame durations. The buffer interface may include an uplink channel handler and a downlink channel handler. The uplink channel handler may be to receive data samples from the first interfaces at first data widths and provide the data samples to the bus interface at third data widths. The downlink channel handler may be to receive processed data samples from the bus interface at third data widths and provide the processed data samples to the second interfaces at second data widths. The bus interface to communicate at a third data width via a third interconnect for operative coupling with allocated memory region utilized by the system to process data samples.

公开(公告)号：US11698872B2

公开(公告)日：2023-07-11

申请号：US17457185

申请日：2021-12-01

Applicant: Microchip Technology Incorporated

Inventor： Narendra Raj S V ,  Priyank Gupta ,  Michael Simmons

IPC: G06F13/16 ,  G06F3/06 ,  G06F5/06 ,  G06F13/28

CPC classification number: G06F13/1673 ,  G06F3/061 ,  G06F3/0631 ,  G06F3/0647 ,  G06F3/0679 ,  G06F5/06 ,  G06F13/28

Abstract: Disclosed examples include an apparatus. The apparatus may include first interfaces, second interfaces, a bus interface, and a buffer interface. The first interfaces may be to communicate at first data widths via first interconnects for operable coupling with data samples sources. The second interface may be to communicate at second data widths via second interconnects for operable coupling with data sinks. The buffer interface may be to communicate with a system to process data samples sampled using different sampling rates according to processing frame durations. The buffer interface may include an uplink channel handler and a downlink channel handler. The uplink channel handler may be to receive data samples from the first interfaces at first data widths and provide the data samples to the bus interface at third data widths. The downlink channel handler may be to receive processed data samples from the bus interface at third data widths and provide the processed data samples to the second interfaces at second data widths. The bus interface to communicate at a third data width via a third interconnect for operative coupling with allocated memory region utilized by the system to process data samples.

公开(公告)号：US11221976B2

公开(公告)日：2022-01-11

申请号：US16258171

申请日：2019-01-25

Applicant: Microchip Technology Incorporated

Inventor： Narendra Raj S V ,  Priyank Gupta ,  Michael Simmons

IPC: G06F13/16 ,  G06F3/06 ,  G06F5/06 ,  G06F1/28 ,  G06F13/28

Abstract: A buffer interface, data transport method, and computing system are described in which a buffer interface may be configured for communicating data samples to and from frame buffers defined in a memory. The configurable buffer interfaces and frame buffers provide a flexible and scalable platform for use with many applications.

公开(公告)号：US20200233714A1

公开(公告)日：2020-07-23

申请号：US16842870

申请日：2020-04-08

Applicant: Microchip Technology Incorporated

Inventor： Michael Simmons ,  Anjana Priya Sistla ,  Priyank Gupta

IPC: G06F9/50 ,  G06F8/41 ,  G06F9/54 ,  G06F12/02

Abstract: An apparatus includes processing cores, memory blocks, a connection between each of processing core and memory block, chip selection circuit, and chip selection circuit busses between the chip selection circuit and each of the memory blocks. Each memory block includes a data port and a memory check port. The chip selection circuit is configured to enable writing data from a highest priority core through respective data ports of the memory blocks. The chip selection circuit is further configured to enable writing data from other cores through respective memory check ports of the memory blocks.