公开(公告)号：US20230231938A1

公开(公告)日：2023-07-20

申请号：US18125857

申请日：2023-03-24

Applicant: Microchip Technology Incorporated

Inventor： William Mahany ,  Ian Saturley ,  Lakshmi Narasimhan ,  Riyas Kattukandan ,  Ramya Kuppusamy ,  Robert Zakowicz

IPC: H04L69/22 ,  G06F9/4401 ,  H04J3/06 ,  H04L12/10

CPC classification number: H04L69/22 ,  G06F9/4418 ,  H04J3/0658 ,  H04L12/10

Abstract: An EtherCAT device is disclosed. The EtherCAT device comprises a data input port to receive a signal representing data, the signal representing one of a plurality of possible logical values; and a degradation calculation circuit. The degradation calculation circuit is to read, demodulate, and convert the received signal into a digital domain representation; process the digital domain representation into slices, where the value of the received signal at a respective time is represented in a respective one of the slices; determine differences between the respective slices and reference slices; identify an intended logical value of the received signal responsive to the determined differences; determine a quantification of error at the respective time responsive to the identified logical value and the determined differences; and determine a signal quality index responsive to the determined quantification of error.

公开(公告)号：US20210136185A1

公开(公告)日：2021-05-06

申请号：US17030439

申请日：2020-09-24

Applicant: Microchip Technology Incorporated

Inventor： William Mahany ,  Ian Saturley ,  Lakshmi Narasimhan ,  Riyas Kattukandan ,  Ramya Kuppusamy ,  Robert Zakowicz

IPC: H04L29/06 ,  H04L12/10 ,  H04J3/06 ,  G06F9/4401

Abstract: An EtherCAT device includes a communications circuit and a wakeup circuit. The wakeup circuit is configured to determine a condition in which to send data to an EtherCAT master node. The wakeup circuit, based on such a condition, is configured to generate a wakeup packet. The communications circuit may be configured to receive an EtherCAT frame originating from the EtherCAT master node. The communications circuit may be configured to populate the EtherCAT frame with the data to be sent to the EtherCAT master node. The communications circuit may be configured to send the EtherCAT frame to the EtherCAT master device.

公开(公告)号：US12126703B2

公开(公告)日：2024-10-22

申请号：US18125820

申请日：2023-03-24

Applicant: Microchip Technology Incorporated

Inventor： William Mahany ,  Ian Saturley ,  Lakshmi Narasimhan ,  Riyas Kattukandan ,  Ramya Kuppusamy ,  Robert Zakowicz

IPC: H04L69/22 ,  G06F9/4401 ,  H04J3/06 ,  H04L12/10

CPC classification number: H04L69/22 ,  G06F9/4418 ,  H04J3/0658 ,  H04L12/10

Abstract: An EtherCAT device with a node for use in an EtherCAT network is disclosed. The EtherCAT device includes: a clock circuit; a clock input to receive an input clock signal; a clock output to send an output clock signal; and control logic. The control logic is to determine whether to operate the EtherCAT device in a clock generation mode or a clock propagation mode, wherein in the clock generation mode, the clock circuit is to drive an oscillator to generate the input clock signal; and in the clock propagation mode, the clock circuit is to receive the input clock signal from another node in the EtherCAT network. The control logic is further to control the clock circuit to output the output clock signal for a subsequent node in the EtherCAT network based upon the input clock signal.

公开(公告)号：US12047480B2

公开(公告)日：2024-07-23

申请号：US18125857

申请日：2023-03-24

Applicant: Microchip Technology Incorporated

Inventor： William Mahany ,  Ian Saturley ,  Lakshmi Narasimhan ,  Riyas Kattukandan ,  Ramya Kuppusamy ,  Robert Zakowicz

IPC: H04L69/22 ,  G06F9/4401 ,  H04J3/06 ,  H04L12/10

CPC classification number: H04L69/22 ,  G06F9/4418 ,  H04J3/0658 ,  H04L12/10

Abstract: An EtherCAT device is disclosed. The EtherCAT device comprises a data input port to receive a signal representing data, the signal representing one of a plurality of possible logical values; and a degradation calculation circuit. The degradation calculation circuit is to read, demodulate, and convert the received signal into a digital domain representation; process the digital domain representation into slices, where the value of the received signal at a respective time is represented in a respective one of the slices; determine differences between the respective slices and reference slices; identify an intended logical value of the received signal responsive to the determined differences; determine a quantification of error at the respective time responsive to the identified logical value and the determined differences; and determine a signal quality index responsive to the determined quantification of error.

公开(公告)号：US20220179997A1

公开(公告)日：2022-06-09

申请号：US17457298

申请日：2021-12-02

Applicant: Microchip Technology Incorporated

Inventor： Brian Branscomb ,  William Mahany ,  Sailesh Rupani

IPC: G06F21/64

Abstract: Examples of the present disclosure relate generally to implementing higher-layer processing on time-sensitive data blocks at a physical-layer-interface device. Some examples include logic to perform operations, the operations including providing data blocks to a physical-layer-interface device. The operations may also include adding dummy data into one or more time-sensitive data blocks of the data blocks being provided to the physical-layer-interface device. A size of the dummy data corresponding to a size of higher-layer-processing data. Other example operations may include removing higher-layer-processing data from a first ingressing data block. The other operations may also include removing a portion of the first ingressing data block and adding the portion to a subsequent ingressing data block. A size of the portion corresponding to the size of integrity-detection data. The other operations may also include removing the integrity-detection data from an ingressing data block. Related methods, systems, and devices are also disclosed.

公开(公告)号：US11924312B2

公开(公告)日：2024-03-05

申请号：US17030439

申请日：2020-09-24

Applicant: Microchip Technology Incorporated

Inventor： William Mahany ,  Ian Saturley ,  Lakshmi Narasimhan ,  Riyas Kattukandan ,  Ramya Kuppusamy ,  Robert Zakowicz

IPC: H04L69/22 ,  G06F9/4401 ,  H04J3/06 ,  H04L12/10

CPC classification number: H04L69/22 ,  G06F9/4418 ,  H04J3/0658 ,  H04L12/10

Abstract: An EtherCAT device includes a communications circuit and a wakeup circuit. The wakeup circuit is configured to determine a condition in which to send data to an EtherCAT master node. The wakeup circuit, based on such a condition, is configured to generate a wakeup packet. The communications circuit may be configured to receive an EtherCAT frame originating from the EtherCAT master node. The communications circuit may be configured to populate the EtherCAT frame with the data to be sent to the EtherCAT master node. The communications circuit may be configured to send the EtherCAT frame to the EtherCAT master device.

公开(公告)号：US20230231937A1

公开(公告)日：2023-07-20

申请号：US18125820

申请日：2023-03-24

Applicant: Microchip Technology Incorporated

Inventor： William Mahany ,  Ian Saturley ,  Lakshmi Narasimhan ,  Riyas Kattukandan ,  Ramya Kuppusamy ,  Robert Zakowicz

IPC: H04L69/22 ,  G06F9/4401 ,  H04J3/06 ,  H04L12/10

CPC classification number: H04L69/22 ,  G06F9/4418 ,  H04J3/0658 ,  H04L12/10

Abstract: An EtherCAT device with a node for use in an EtherCAT network is disclosed. The EtherCAT device includes: a clock circuit; a clock input to receive an input clock signal; a clock output to send an output clock signal; and control logic. The control logic is to determine whether to operate the EtherCAT device in a clock generation mode or a clock propagation mode, wherein in the clock generation mode, the clock circuit is to drive an oscillator to generate the input clock signal; and in the clock propagation mode, the clock circuit is to receive the input clock signal from another node in the EtherCAT network. The control logic is further to control the clock circuit to output the output clock signal for a subsequent node in the EtherCAT network based upon the input clock signal.