公开(公告)号：US20240378113A1

公开(公告)日：2024-11-14

申请号：US18415628

申请日：2024-01-17

Applicant: Micron Technology, Inc.

Inventor： Joseph M. MCCRATE ,  Kirthi SHENOY ,  Marco SFORZIN ,  Brian M. TWAIT

IPC: G06F11/10

Abstract: Provided is a memory system comprising a plurality of memory components. The ECC decoding is configured to construct first and second codewords from a single set of data within the plurality of memory components and perform error correction code (ECC) decoding on the first and second codewords received read from the plurality of memory components wherein the ECC decoding is configured to (i) detect random errors in the first received codeword and (ii) use data associated with the detected random errors to correct erasures in the second received codeword.

公开(公告)号：US20250045153A1

公开(公告)日：2025-02-06

申请号：US18786254

申请日：2024-07-26

Applicant: Micron Technology, Inc.

Inventor： Joseph M. McCRATE ,  Kirthi SHENOY ,  Marco SFORZIN ,  Brian M. TWAIT

IPC: G06F11/10

Abstract: Provided herein is a memory system including logical to physical memory address translation logic to build up a minimum address space containing a memory device address with defects, the translation being based on memory correction attempts. For each correction attempt, the logical address is first translated to a memory device physical address and bit positions at the physical address are compared with an existing error bit pattern to determine if marking should be applied to the memory device. If the bit positions do not match the existing error bit pattern, but errors are corrected from the marked memory device, the existing error bit pattern will be updated to reflect a new error bit pattern.

公开(公告)号：US20240296090A1

公开(公告)日：2024-09-05

申请号：US18415627

申请日：2024-01-17

Applicant: Micron Technology, Inc.

Inventor： Joseph M. MCCRATE ,  Kirthi SHENOY ,  Marco SFORZIN ,  Brian M. TWAIT

IPC: G06F11/10

CPC classification number: G06F11/1044

Abstract: Provided is a memory system comprising a plurality of memory components. The ECC decoding is configured to construct first and second codewords from a single set of data within the plurality of memory components and perform error correction code (ECC) decoding on the first and second codewords received read from the plurality of memory components wherein the ECC decoding is configured to (i) detect random errors in the first received codeword and (ii) use data associated with the detected random errors to correct erasures in the second received codeword.

公开(公告)号：US20240378114A1

公开(公告)日：2024-11-14

申请号：US18415631

申请日：2024-01-17

Applicant: Micron Technology, Inc.

Inventor： Joseph M. MCCRATE ,  Kirthi SHENOY ,  Marco SFORZIN ,  Brian M. TWAIT

IPC: G06F11/10

Abstract: Provided is a memory system comprising a plurality of memory components. The ECC decoding is configured to construct first and second codewords from a single set of data within the plurality of memory components and perform error correction code (ECC) decoding on the first and second codewords received read from the plurality of memory components wherein the ECC decoding is configured to (i) detect random errors in the first received codeword and (ii) use data associated with the detected random errors to correct erasures in the second received codeword.

公开(公告)号：US20240297668A1

公开(公告)日：2024-09-05

申请号：US18415626

申请日：2024-01-17

Applicant: Micron Technology, Inc.

Inventor： Joseph M. MCCRATE ,  Kirthi SHENOY ,  Marco SFORZIN ,  Brian M. TWAIT

IPC: H03M13/37 ,  G06F11/10 ,  H03M13/15

CPC classification number: H03M13/373 ,  G06F11/1044 ,  H03M13/1575

Abstract: Provided is a memory system comprising a plurality of memory components. The ECC decoding is configured to construct first and second codewords from a single set of data within the plurality of memory components and perform error correction code (ECC) decoding on the first and second codewords received read from the plurality of memory components wherein the ECC decoding is configured to (i) detect random errors in the first received codeword and (ii) use data associated with the detected random errors to correct erasures in the second received codeword.

公开(公告)号：US20240345920A1

公开(公告)日：2024-10-17

申请号：US18415634

申请日：2024-01-17

Applicant: Micron Technology, Inc.

Inventor： Joseph M. MCCRATE ,  Kirthi SHENOY ,  Marco SFORZIN ,  Brian M. TWAIT

IPC: G06F11/10

CPC classification number: G06F11/1068 ,  G06F11/1004

Abstract: Provided is an apparatus comprising a search engine configured to (i) receive parallel input of a set of syndrome polynomial products corresponding to a set of ECC words and (ii) produce corresponding sets of polynomial roots therefrom and a sequence detector configured to identify sequences within each of the polynomial roots within the set of roots. Also provided is sequence check logic for (i) combining the identified sequences within each of the polynomial roots and (ii) performing a sequence check of the combined identified sequences to determine whether only one of the identified sequences if valid; and an error location generator to derive an error location in each of the ECC words within the set responsive to the valid sequence.

公开(公告)号：US20240272981A1

公开(公告)日：2024-08-15

申请号：US18415632

申请日：2024-01-17

Applicant: Micron Technology, Inc.

Inventor： Joseph M. MCCRATE ,  Kirthi SHENOY ,  Marco SFORZIN ,  Brian M. TWAIT

IPC: G06F11/10

CPC classification number: G06F11/1016 ,  G06F11/1068

Abstract: Provided is an apparatus comprising a search engine configured to (i) receive parallel input of a set of syndrome polynomial products corresponding to a set of ECC words and (ii) produce corresponding sets of polynomial roots therefrom and a sequence detector configured to identify sequences within each of the polynomial roots within the set of roots. Also provided is sequence check logic for (i) combining the identified sequences within each of the polynomial roots and (ii) performing a sequence check of the combined identified sequences to determine whether only one of the identified sequences if valid; and an error location generator to derive an error location in each of the ECC words within the set responsive to the valid sequence.