公开(公告)号：US20220101898A1

公开(公告)日：2022-03-31

申请号：US17545888

申请日：2021-12-08

Applicant: Micron Technology, Inc.

Inventor： Agatino Massimo Maccarrone ,  Luigi Pilolli ,  Ali Feiz Zarrin Ghalam ,  Chin Yu Chen

IPC: G11C7/22 ,  G11C7/10

Abstract: Disclosed are systems and methods involving memory-side write training to improve data valid window. In one implementation, a method for performing memory-side write training may comprise delaying a rising edge or a falling edge of a first data signal, delaying a rising edge or a falling edge of a second data signal, and aligning the two adjusted signals to reduce a window of time that the data signals are not valid and thereby improve or optimize the data valid window (DVW) of a memory array. According to implementations herein, various edges of data signals and clock signals may be adjusted or delayed via dedicated trim cells or circuitry present in the data paths located on the memory side of a system.

公开(公告)号：US11848071B2

公开(公告)日：2023-12-19

申请号：US17545888

申请日：2021-12-08

Applicant: Micron Technology, Inc.

Inventor： Agatino Massimo Maccarrone ,  Luigi Pilolli ,  Ali Feiz Zarrin Ghalam ,  Chin Yu Chen

IPC: G11C8/00 ,  G11C7/22 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/1087 ,  G11C7/1093 ,  G11C2207/2254

Abstract: Disclosed are systems and methods involving memory-side write training to improve data valid window. In one implementation, a method for performing memory-side write training may comprise delaying a rising edge or a falling edge of a first data signal, delaying a rising edge or a falling edge of a second data signal, and aligning the two adjusted signals to reduce a window of time that the data signals are not valid and thereby improve or optimize the data valid window (DVW) of a memory array. According to implementations herein, various edges of data signals and clock signals may be adjusted or delayed via dedicated trim cells or circuitry present in the data paths located on the memory side of a system.

公开(公告)号：US11211104B2

公开(公告)日：2021-12-28

申请号：US17092046

申请日：2020-11-06

Applicant: Micron Technology, Inc.

Inventor： Agatino Massimo Maccarrone ,  Luigi Pilolli ,  Ali Feiz Zarrin Ghalam ,  Chin Yu Chen

IPC: G11C8/00 ,  G11C7/22 ,  G11C7/10

Abstract: Disclosed are systems and methods involving memory-side write training to improve data valid window. In one implementation, a method for performing memory-side write training may comprise delaying a rising edge or a falling edge of a first data signal, delaying a rising edge or a falling edge of a second data signal, and aligning the two adjusted signals to reduce a window of time that the data signals are not valid and thereby improve or optimize the data valid window (DVW) of a memory array. According to implementations herein, various edges of data signals and clock signals may be adjusted or delayed via dedicated trim cells or circuitry present in the data paths located on the memory side of a system.

公开(公告)号：US20210057007A1

公开(公告)日：2021-02-25

申请号：US17092046

申请日：2020-11-06

Applicant: Micron Technology, Inc.

Inventor： Agatino Massimo Maccarrone ,  Luigi Pilolli ,  Ali Feiz Zarrin Ghalam ,  Chin Yu Chen

IPC: G11C7/22 ,  G11C7/10

Abstract: Disclosed are systems and methods involving memory-side write training to improve data valid window. In one implementation, a method for performing memory-side write training may comprise delaying a rising edge or a falling edge of a first data signal, delaying a rising edge or a falling edge of a second data signal, and aligning the two adjusted signals to reduce a window of time that the data signals are not valid and thereby improve or optimize the data valid window (DVW) of a memory array. According to implementations herein, various edges of data signals and clock signals may be adjusted or delayed via dedicated trim cells or circuitry present in the data paths located on the memory side of a system.

公开(公告)号：US10861517B1

公开(公告)日：2020-12-08

申请号：US16447727

申请日：2019-06-20

Applicant: Micron Technology, Inc.

Inventor： Agatino Massimo Maccarrone ,  Luigi Pilolli ,  Ali Feiz Zarrin Ghalam ,  Chin Yu Chen

IPC: G11C7/10 ,  G11C7/22

Abstract: Disclosed are systems and methods involving memory-side write training to improve data valid window. In one implementation, a method for performing memory-side write training may comprise delaying a rising edge or a falling edge of a first data signal, delaying a rising edge or a falling edge of a second data signal, and aligning the two adjusted signals to reduce a window of time that the data signals are not valid and thereby improve or optimize the data valid window (DVW) of a memory array. According to implementations herein, various edges of data signals and clock signals may be adjusted or delayed via dedicated trim cells or circuitry present in the data paths located on the memory side of a system.