公开(公告)号：US20240419534A1

公开(公告)日：2024-12-19

申请号：US18819616

申请日：2024-08-29

Applicant: Micron Technology, Inc.

Inventor： Christopher Baronne

IPC: G06F11/07 ,  G06F9/38

Abstract: Devices and techniques for parking threads in a barrel processor for managing hazard clearing are described herein. A barrel processor includes hazard management circuitry that is used to receive an indication of an instruction executing in a compute pipeline of the barrel processor, the instruction having encountered a hazard and unable to progress through the compute pipeline; store the indication of the instruction in a hazard memory; receive a signal indicating that the hazard has cleared; and cause the instruction to be rescheduled at the beginning of the compute pipeline in response to the signal.

公开(公告)号：US11586443B2

公开(公告)日：2023-02-21

申请号：US17074730

申请日：2020-10-20

Applicant: Micron Technology, Inc.

Inventor： Christopher Baronne ,  Dean E. Walker

IPC: G06F9/38 ,  G06F9/30

Abstract: Devices and techniques for thread-based processor halting are described herein. A processor monitors control-status register (CSR) values that correspond to a halt condition for a thread. The processor then compares the halt condition to a current state of the thread and halts in response to the current state of the thread meeting the halt condition.

公开(公告)号：US12235774B2

公开(公告)日：2025-02-25

申请号：US18444148

申请日：2024-02-16

Applicant: Micron Technology, Inc.

Inventor： Christopher Baronne

IPC: G06F12/126

Abstract: Devices and techniques for parking threads in a barrel processor for managing cache eviction requests are described herein. A barrel processor includes eviction circuitry and is configured to perform operations to: (a) detect a thread that includes a memory access operation, the thread entering a memory request pipeline of the barrel processor; (b) determine that a data cache line has to be evicted from a data cache for the thread to perform the memory access operation; (c) copy the thread into a park queue; (d) evict a data cache line from the data cache; (e) identify an empty cycle in the memory request pipeline; (f) schedule the thread to execute during the empty cycle; and (g) remove the thread from the park queue.

公开(公告)号：US11940928B2

公开(公告)日：2024-03-26

申请号：US17897913

申请日：2022-08-29

Applicant: Micron Technology, Inc.

Inventor： Christopher Baronne

IPC: G06F12/126

CPC classification number: G06F12/126 ,  G06F2212/1044

Abstract: Devices and techniques for parking threads in a barrel processor for managing cache eviction requests are described herein. A barrel processor includes eviction circuitry and is configured to perform operations to: (a) detect a thread that includes a memory access operation, the thread entering a memory request pipeline of the barrel processor; (b) determine that a data cache line has to be evicted from a data cache for the thread to perform the memory access operation; (c) copy the thread into a park queue; (d) evict a data cache line from the data cache; (e) identify an empty cycle in the memory request pipeline; (f) schedule the thread to execute during the empty cycle; and (g) remove the thread from the park queue.

公开(公告)号：US20230333894A1

公开(公告)日：2023-10-19

申请号：US17721578

申请日：2022-04-15

Applicant: Micron Technology, Inc.

Inventor： Christopher Baronne ,  Tony M. Brewer

IPC: G06F9/50 ,  G06F9/30

CPC classification number: G06F9/5016 ,  G06F9/5022 ,  G06F9/3009

Abstract: Disclosed in some examples are methods, systems, devices, and machine-readable mediums which utilize a pool method whereby a host process executing on the host processor reserves one or more pools of memory for worker threads of the host process. Upon creation of a new thread corresponding to the host process, the worker processor executing the new thread may assign a portion of the previously reserved pool to the new thread. By giving some control to a worker processor to assign memory from a previously reserved pool, threads may be assigned memory resources without additional message overhead from the host processor to the worker processor while at the same time retaining overall memory control with the host processor.

公开(公告)号：US12197351B2

公开(公告)日：2025-01-14

申请号：US17813780

申请日：2022-07-20

Applicant: Micron Technology, Inc.

Inventor： Christopher Baronne ,  Tony M. Brewer

IPC: G06F13/16 ,  G06F13/40

Abstract: Various examples are directed to systems and methods for requesting an atomic operation. A first hardware compute element may send a first request via a network structure, where the first request comprises an atomic opcode indicating an atomic operation to be performed by a second hardware compute element. The network structure may provide an address bus from the first hardware compute element for providing the atomic opcode to the second hardware compute element. The second hardware compute element may execute the atomic operation and send confirmation data indicating completion of the atomic operation. The network structure may provide a second bus from the second hardware compute element and the first hardware compute element. The second bus may be for providing the confirmation data from the second hardware compute element to the first hardware compute element.

公开(公告)号：US12099402B2

公开(公告)日：2024-09-24

申请号：US17897926

申请日：2022-08-29

Applicant: Micron Technology, Inc.

Inventor： Christopher Baronne

IPC: G06F11/00 ,  G06F9/38 ,  G06F11/07

CPC classification number: G06F11/0793 ,  G06F9/3861 ,  G06F11/0721

Abstract: Devices and techniques for parking threads in a barrel processor for managing hazard clearing are described herein. A barrel processor includes hazard management circuitry that is used to receive an indication of an instruction executing in a compute pipeline of the barrel processor, the instruction having encountered a hazard and unable to progress through the compute pipeline; store the indication of the instruction in a hazard memory; receive a signal indicating that the hazard has cleared; and cause the instruction to be rescheduled at the beginning of the compute pipeline in response to the signal.

公开(公告)号：US20240241836A1

公开(公告)日：2024-07-18

申请号：US18444148

申请日：2024-02-16

Applicant: Micron Technology, Inc.

Inventor： Christopher Baronne

IPC: G06F12/126

CPC classification number: G06F12/126 ,  G06F2212/1044

Abstract: Devices and techniques for parking threads in a barrel processor for managing cache eviction requests are described herein. A barrel processor includes eviction circuitry and is configured to perform operations to: (a) detect a thread that includes a memory access operation, the thread entering a memory request pipeline of the barrel processor; (b) determine that a data cache line has to be evicted from a data cache for the thread to perform the memory access operation; (c) copy the thread into a park queue; (d) evict a data cache line from the data cache; (e) identify an empty cycle in the memory request pipeline; (f) schedule the thread to execute during the empty cycle; and (g) remove the thread from the park queue.

公开(公告)号：US20240070088A1

公开(公告)日：2024-02-29

申请号：US17897913

申请日：2022-08-29

Applicant: Micron Technology, Inc.

Inventor： Christopher Baronne

IPC: G06F12/126

CPC classification number: G06F12/126 ,  G06F2212/1044

Abstract: Devices and techniques for parking threads in a barrel processor for managing cache eviction requests are described herein. A barrel processor includes eviction circuitry and is configured to perform operations to: (a) detect a thread that includes a memory access operation, the thread entering a memory request pipeline of the barrel processor; (b) determine that a data cache line has to be evicted from a data cache for the thread to perform the memory access operation; (c) copy the thread into a park queue; (d) evict a data cache line from the data cache; (e) identify an empty cycle in the memory request pipeline; (f) schedule the thread to execute during the empty cycle; and (g) remove the thread from the park queue.

公开(公告)号：US20240070011A1

公开(公告)日：2024-02-29

申请号：US17897926

申请日：2022-08-29

Applicant: Micron Technology, Inc.

Inventor： Christopher Baronne

IPC: G06F11/07 ,  G06F9/38

CPC classification number: G06F11/0793 ,  G06F9/3861 ,  G06F11/0721

Abstract: Devices and techniques for parking threads in a barrel processor for managing hazard clearing are described herein. A barrel processor includes hazard management circuitry that is used to receive an indication of an instruction executing in a compute pipeline of the barrel processor, the instruction having encountered a hazard and unable to progress through the compute pipeline; store the indication of the instruction in a hazard memory; receive a signal indicating that the hazard has cleared; and cause the instruction to be rescheduled at the beginning of the compute pipeline in response to the signal.