公开(公告)号：US20240393983A1

公开(公告)日：2024-11-28

申请号：US18795877

申请日：2024-08-06

Applicant: Micron Technology, Inc.

Inventor： Tony M. Brewer ,  Dean E. Walker

IPC: G06F3/06 ,  G06F9/38

Abstract: System and techniques for host-preferred memory operation are described herein. At a memory-side cache of a memory device that includes accelerator hardware, a first memory operation can be received from a host. A determination that the first memory operation corresponds to a cache set based on an address of the first memory operation is made. A second memory operation can be received from the accelerator hardware. Another determination can be made that the second memory operation corresponds to the cache set. Here, the first memory operation can be enqueued in a host queue of the cache set and the second memory operation can be enqueued in an internal request queue of the cache set. The first memory operation and the second memory operation can be executed as each is dequeued.

公开(公告)号：US12135987B2

公开(公告)日：2024-11-05

申请号：US17075096

申请日：2020-10-20

Applicant: Micron Technology, Inc.

Inventor： Chris Baronne ,  Dean E. Walker ,  John Amelio

IPC: G06F9/48 ,  G06F9/30 ,  G11C7/10 ,  G11C7/22

Abstract: Devices and techniques for sharing thread memory in a barrel processor via scheduling are described herein. An apparatus includes a barrel processor, which includes thread scheduling circuitry, where the barrel processor is configured to perform operations through use of the thread scheduling circuitry, the operations including those to: place a thread to be scheduled in one of two groups: a first group and a second group, wherein the first group is associated with a first processor storage device, and the second group is associated with a second processor storage device; and schedule a current thread to place into a pipeline for the barrel processor, the scheduling performed by alternating between threads in the first group and threads in the second group.

公开(公告)号：US20240069801A1

公开(公告)日：2024-02-29

申请号：US17823391

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Tony M. Brewer ,  Dean E. Walker

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: Systems and techniques for a memory-side cache directory-based request queue are described herein. A memory request is received at an interface of a memory device. One or more fields of the memory request are written into an entry of a directory data structure. The identifier of the entry is pushed onto a queue. To perform the memory request, the identifier is popped off of the queue and a field of the memory request is retrieved from the entry of the directory data structure using the identifier. Then, a process on the memory request can be performed using the field retrieved from the entry of the directory data structure.

公开(公告)号：US20240069800A1

公开(公告)日：2024-02-29

申请号：US17823314

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Tony M. Brewer ,  Dean E. Walker

IPC: G06F3/06 ,  G06F9/38

CPC classification number: G06F3/0659 ,  G06F3/0607 ,  G06F9/3877 ,  G06F3/0679

Abstract: System and techniques for host-preferred memory operation are described herein. At a memory-side cache of a memory device that includes accelerator hardware, a first memory operation can be received from a host. A determination that the first memory operation corresponds to a cache set based on an address of the first memory operation is made. A second memory operation can be received from the accelerator hardware. Another determination can be made that the second memory operation corresponds to the cache set. Here, the first memory operation can be enqueued in a host queue of the cache set and the second memory operation can be enqueued in an internal request queue of the cache set. The first memory operation and the second memory operation can be executed as each is dequeued.

公开(公告)号：US11734173B2

公开(公告)日：2023-08-22

申请号：US17854770

申请日：2022-06-30

Applicant: Micron Technology, Inc.

Inventor： Tony Brewer ,  Dean E. Walker ,  Chris Baronne

IPC: G06F12/00 ,  G06F12/06 ,  G06F12/02 ,  G06F12/0844

CPC classification number: G06F12/0607 ,  G06F12/0223 ,  G06F12/0844 ,  G06F2212/1012

Abstract: Devices and techniques for memory access bounds checking for a programmable atomic operator are described herein. A processor can execute a programmable atomic operator with a base memory address. The processor can obtain a memory interleave size indicator corresponding to the programmable atomic operator and calculate a contiguous memory address range from the base memory address and the memory interleave size. The processor can then detect that a memory request from the programmable atomic operator is outside the contiguous memory address range and deny the memory request when it is outside of the contiguous memory address range and allow the memory request otherwise.

公开(公告)号：US11698791B2

公开(公告)日：2023-07-11

申请号：US17880230

申请日：2022-08-03

Applicant: Micron Technology, Inc.

Inventor： Dean E. Walker ,  Tony Brewer ,  Chris Baronne

IPC: G06F9/4401 ,  G06F12/14

CPC classification number: G06F9/4403 ,  G06F12/1458 ,  G06F12/14 ,  G06F2212/1052 ,  Y02D10/00

Abstract: Devices and techniques for on-demand programmable atomic kernel loading are described herein. A programmable atomic unit (PAU) of a memory controller can receive an invocation of a programmable atomic operator by the memory controller. The PAU can then perform a verification on a programmable atomic operator partition for the programmable atomic operator. Here, the programmable atomic operator partition is located in a memory of the PAU. The PAU can then signal a trap in response to the verification indicating that the programmable atomic operator partition is not prepared.

公开(公告)号：US11669486B2

公开(公告)日：2023-06-06

申请号：US17572240

申请日：2022-01-10

Applicant: Micron Technology, Inc.

Inventor： Dean E. Walker ,  Tony M. Brewer

IPC: G06F13/42 ,  G06F13/20 ,  H01L23/538

CPC classification number: G06F13/4282 ,  G06F13/20 ,  G06F13/423 ,  G06F2213/0002 ,  H01L23/538

Abstract: A system comprises an interposer including interconnect and multiple chiplets arranged on the interposer. Each chiplet includes multiple chiplet input-output (I/O) channels interconnected to I/O channels of other chiplets by the interposer; a chiplet I/O interface for the chiplet I/O channels that includes multiple interface layers; and initialization logic circuitry configured to advance initialization of the chiplet interface sequentially through the interface layers starting with a lowest interface layer.

公开(公告)号：US20220414004A1

公开(公告)日：2022-12-29

申请号：US17854770

申请日：2022-06-30

Applicant: Micron Technology, Inc.

Inventor： Tony Brewer ,  Dean E. Walker ,  Chris Baronne

IPC: G06F12/06 ,  G06F12/02

Abstract: Devices and techniques for memory access bounds checking for a programmable atomic operator are described herein. A processor can execute a programmable atomic operator with a base memory address. The processor can obtain a memory interleave size indicator corresponding to the programmable atomic operator and calculate a contiguous memory address range from the base memory address and the memory interleave size. The processor can then detect that a memory request from the programmable atomic operator is outside the contiguous memory address range and deny the memory request when it is outside of the contiguous memory address range and allow the memory request otherwise.

公开(公告)号：US11507453B2

公开(公告)日：2022-11-22

申请号：US17074958

申请日：2020-10-20

Applicant: Micron Technology, Inc.

Inventor： Dean E. Walker ,  Chris Baronne

IPC: G06F11/00 ,  G06F11/10 ,  G06F9/30

Abstract: To implement low-latency register error correction a register may be read as part of an instruction when that instruction is the currently executing instruction in a processor. A correctable error in data produced from reading the register can be detected. In response to detecting the correctable error, the currently executing instruction in the processor can be changed into a register update instruction that is executed to overwrite the data in the register with corrected data. Then, the original (e.g., unchanged) instruction can be rescheduled.

公开(公告)号：US20220138142A1

公开(公告)日：2022-05-05

申请号：US17572240

申请日：2022-01-10

Applicant: Micron Technology, Inc.

Inventor： Dean E. Walker ,  Tony M. Brewer

IPC: G06F13/42 ,  G06F13/20

Abstract: A system comprises an interposer including interconnect and multiple chiplets arranged on the interposer. Each chiplet includes multiple chiplet input-output (I/O) channels interconnected to I/O channels of other chiplets by the interposer; a chiplet I/O interface for the chiplet I/O channels that includes multiple interface layers; and initialization logic circuitry configured to advance initialization of the chiplet interface sequentially through the interface layers starting with a lowest interface layer.