公开(公告)号：US11538508B2

公开(公告)日：2022-12-27

申请号：US17137975

申请日：2020-12-30

Applicant: Micron Technology, Inc.

Inventor： Jasper S. Gibbons ,  Matthew A. Prather ,  Brent Keeth ,  Frank F Ross ,  Daniel Benjamin Stewart ,  Randall J. Rooney

IPC: G11C7/10 ,  G11C7/22

Abstract: The present disclosure provides techniques for using a multiple-port buffer to improve a transaction rate of a memory module. In an example, a memory module can include a circuit board having an external interface, first memory devices mounted to the circuit board, and a first multiple-port buffer circuit mounted to the circuit board. The first multiple-port buffer circuit can include a first port coupled to data lines of the external interface, the first port configured to operate at a first transaction rate, a second port coupled to data lines of a first plurality of the first memory devices, and a third port coupled to data lines of a second plurality of the first memory devices. The second and third ports can be configured to operate at a second transaction rate, wherein the second transaction rate is slower than the first transaction rate.

公开(公告)号：US12300349B2

公开(公告)日：2025-05-13

申请号：US18087328

申请日：2022-12-22

Applicant: Micron Technology, Inc.

Inventor： Jasper S. Gibbons ,  Matthew A. Prather ,  Brent Keeth ,  Frank F Ross ,  Daniel Benjamin Stewart ,  Randall J. Rooney

IPC: G11C7/10 ,  G11C7/22

Abstract: The present disclosure provides techniques for using a multiple-port buffer to improve a transaction rate of a memory module. In an example, a memory module can include a circuit board having an external interface, first memory devices mounted to the circuit board, and a first multiple-port buffer circuit mounted to the circuit board. The first multiple-port buffer circuit can include a first port coupled to data lines of the external interface, the first port configured to operate at a first transaction rate, a second port coupled to data lines of a first plurality of the first memory devices, and a third port coupled to data lines of a second plurality of the first memory devices. The second and third ports can be configured to operate at a second transaction rate, wherein the second transaction rate is slower than the first transaction rate.

公开(公告)号：US20230127970A1

公开(公告)日：2023-04-27

申请号：US18087328

申请日：2022-12-22

Applicant: Micron Technology, Inc.

Inventor： Jasper S. Gibbons ,  Matthew A. Prather ,  Brent Keeth ,  Frank F. Ross ,  Daniel Benjamin Stewart ,  Randall J. Rooney

IPC: G11C7/10 ,  G11C7/22

Abstract: The present disclosure provides techniques for using a multiple-port buffer to improve a transaction rate of a memory module. In an example, a memory module can include a circuit board having an external interface, first memory devices mounted to the circuit board, and a first multiple-port buffer circuit mounted to the circuit board. The first multiple-port buffer circuit can include a first port coupled to data lines of the external interface, the first port configured to operate at a first transaction rate, a second port coupled to data lines of a first plurality of the first memory devices, and a third port coupled to data lines of a second plurality of the first memory devices. The second and third ports can be configured to operate at a second transaction rate, wherein the second transaction rate is slower than the first transaction rate.